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authorClifford Wolf <clifford@clifford.at>2014-08-16 23:50:36 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-16 23:50:36 +0200
commit7f734ecc098a2a113ced835cefc9d4e1982f08d0 (patch)
tree0e73ad74bd4602da7a6a1a3b264e1842deccac18 /frontends
parentf82c978e08604c596b034fb6e74ac34c78b9364b (diff)
Added module->uniquify()
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verific/verific.cc8
1 files changed, 2 insertions, 6 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 95b3c407..0440f88e 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -603,9 +603,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
// log(" importing net %s.\n", net->Name());
- std::string wire_name = RTLIL::escape_id(net->Name());
- while (module->count_id(wire_name))
- wire_name += "_";
+ RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(net->Name()));
RTLIL::Wire *wire = module->addWire(wire_name);
import_attributes(wire->attributes, net);
@@ -627,9 +625,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
{
// log(" importing netbus %s.\n", netbus->Name());
- std::string wire_name = RTLIL::escape_id(netbus->Name());
- while (module->count_id(wire_name))
- wire_name += "_";
+ RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(netbus->Name()));
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = std::min(netbus->LeftIndex(), netbus->RightIndex());
import_attributes(wire->attributes, netbus);