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authorClifford Wolf <clifford@clifford.at>2013-11-24 20:29:07 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 20:29:07 +0100
commit8dafecd34d772b1d9ec190b39913b236cdc8fb17 (patch)
tree263b31c6aaa6ef8df765a2ad8c66212b414d793f /frontends
parent4011d476469a761ed05f91d11935f8ad07f901ba (diff)
Added module->avail_parameters (for advanced techmap features)
Diffstat (limited to 'frontends')
-rw-r--r--frontends/ast/genrtlil.cc6
1 files changed, 5 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 66b670c7..f7e7b852 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -805,7 +805,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_TASK:
case AST_FUNCTION:
case AST_AUTOWIRE:
- case AST_PARAMETER:
case AST_LOCALPARAM:
case AST_DEFPARAM:
case AST_GENVAR:
@@ -814,6 +813,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_GENIF:
break;
+ // remember the parameter, needed for example in techmap
+ case AST_PARAMETER:
+ current_module->avail_parameters.insert(str);
+ break;
+
// create an RTLIL::Wire for an AST_WIRE node
case AST_WIRE: {
if (current_module->wires.count(str) != 0)