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authorClifford Wolf <clifford@clifford.at>2014-06-14 07:44:19 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-14 07:44:19 +0200
commit9dd16fa41c01c8da2e4905184cce0391a7547fa3 (patch)
treefa7a48f2f759664ad0b9f8e51b6621e555a4f5f8 /frontends
parent7ef0da32cdcddb50de8ba8acf0c6421fe5732c55 (diff)
Added real->int convertion in ast genrtlil
Diffstat (limited to 'frontends')
-rw-r--r--frontends/ast/genrtlil.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 9273636f..5b43f57f 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -602,6 +602,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
sign_hint = false;
break;
+ case AST_REALVALUE:
+ width_hint = std::max(width_hint, 32);
+ break;
+
case AST_IDENTIFIER:
id_ast = id2ast;
if (id_ast == NULL && current_scope.count(str))
@@ -909,6 +913,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
return RTLIL::SigSpec(bitsAsConst());
}
+ case AST_REALVALUE:
+ {
+ int intvalue = round(realvalue);
+ log("Warning: converting real value %e to integer %d at %s:%d.\n",
+ realvalue, intvalue, filename.c_str(), linenum);
+ return RTLIL::SigSpec(intvalue);
+ }
+
// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
// for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
// shifter cell is created and the output signal of this cell is returned