diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:15:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (patch) | |
| tree | 27801c4b0171a2491ff6817ebb6d2a1d1484c086 /kernel/bitpattern.h | |
| parent | 16e5ae0b92ac4b7568cb11a769e612e152c0042e (diff) | |
SigSpec refactoring: using the accessor functions everywhere
Diffstat (limited to 'kernel/bitpattern.h')
| -rw-r--r-- | kernel/bitpattern.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 0ca26bb3..934796d2 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -31,16 +31,16 @@ struct BitPatternPool BitPatternPool(RTLIL::SigSpec sig) { - width = sig.__width; + width = sig.size(); if (width > 0) { std::vector<RTLIL::State> pattern(width); sig.optimize(); for (int i = 0; i < width; i++) { RTLIL::SigSpec s = sig.extract(i, 1); s.optimize(); - assert(s.__chunks.size() == 1); - if (s.__chunks[0].wire == NULL && s.__chunks[0].data.bits[0] <= RTLIL::State::S1) - pattern[i] = s.__chunks[0].data.bits[0]; + assert(s.chunks().size() == 1); + if (s.chunks()[0].wire == NULL && s.chunks()[0].data.bits[0] <= RTLIL::State::S1) + pattern[i] = s.chunks()[0].data.bits[0]; else pattern[i] = RTLIL::State::Sa; } @@ -63,8 +63,8 @@ struct BitPatternPool { sig.optimize(); assert(sig.is_fully_const()); - assert(sig.__chunks.size() == 1); - bits_t bits = sig.__chunks[0].data.bits; + assert(sig.chunks().size() == 1); + bits_t bits = sig.chunks()[0].data.bits; for (auto &b : bits) if (b > RTLIL::State::S1) b = RTLIL::State::Sa; |