diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /kernel/celltypes.h | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'kernel/celltypes.h')
| -rw-r--r-- | kernel/celltypes.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index d3c848f4..20d68d55 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -171,7 +171,7 @@ struct CellTypes if (cell_types.count(type) > 0) return true; for (auto design : designs) - if (design->modules.count(type) > 0) + if (design->modules_.count(type) > 0) return true; return false; } @@ -180,9 +180,9 @@ struct CellTypes { if (cell_types.count(type) == 0) { for (auto design : designs) - if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires_.count(port)) - return design->modules.at(type)->wires_.at(port)->port_output; + if (design->modules_.count(type) > 0) { + if (design->modules_.at(type)->wires_.count(port)) + return design->modules_.at(type)->wires_.at(port)->port_output; return false; } return false; @@ -203,9 +203,9 @@ struct CellTypes { if (cell_types.count(type) == 0) { for (auto design : designs) - if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires_.count(port)) - return design->modules.at(type)->wires_.at(port)->port_input; + if (design->modules_.count(type) > 0) { + if (design->modules_.at(type)->wires_.count(port)) + return design->modules_.at(type)->wires_.at(port)->port_input; return false; } return false; |