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authorRuben Undheim <ruben.undheim@gmail.com>2018-08-30 20:46:22 +0200
committerRuben Undheim <ruben.undheim@gmail.com>2018-08-30 20:46:22 +0200
commit78bfe0de96fa5c6a7e53689ef53deaeac1d0a7b8 (patch)
treecc36d8cc573f1e6cc9b15ccc85a66883356cbf5f /kernel/consteval.h
parent291bd6d9b3f51ea86c38bbe998c0896ad8b9fed2 (diff)
parent5033b51947a6ef02cb785b5622e993335efa750a (diff)
Merge tag 'upstream/0.7+20180830git0b7a184'
Upstream version 0.7+20180830git0b7a184
Diffstat (limited to 'kernel/consteval.h')
-rw-r--r--kernel/consteval.h9
1 files changed, 8 insertions, 1 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 4d48b45e..0229f504 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -36,8 +36,9 @@ struct ConstEval
SigSet<RTLIL::Cell*> sig2driver;
std::set<RTLIL::Cell*> busy;
std::vector<SigMap> stack;
+ RTLIL::State defaultval;
- ConstEval(RTLIL::Module *module) : module(module), assign_map(module)
+ ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)
{
CellTypes ct;
ct.setup_internals();
@@ -365,6 +366,12 @@ struct ConstEval
if (sig.is_fully_const())
return true;
+ if (defaultval != RTLIL::State::Sm) {
+ for (auto &bit : sig)
+ if (bit.wire) bit = defaultval;
+ return true;
+ }
+
for (auto &c : sig.chunks())
if (c.wire != NULL)
undef.append(c);