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authorClifford Wolf <clifford@clifford.at>2014-01-03 17:30:50 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-03 17:30:50 +0100
commit7354a1718e2e3f2eec4843a56410743af0ff7a83 (patch)
tree51fb2734c5119a00f5de5acee456432389a6f2d6 /kernel/consteval.h
parent8a8d444648bd1744c2598854367fd14d143aeb78 (diff)
Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux
Diffstat (limited to 'kernel/consteval.h')
-rw-r--r--kernel/consteval.h10
1 files changed, 6 insertions, 4 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h
index a424007e..10116ccf 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -110,6 +110,7 @@ struct ConstEval
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
{
std::vector<RTLIL::SigSpec> y_candidates;
+ int count_maybe_set_s_bits = 0;
int count_set_s_bits = 0;
for (int i = 0; i < sig_s.width; i++)
@@ -120,16 +121,17 @@ struct ConstEval
if (s_bit == RTLIL::State::Sx || s_bit == RTLIL::State::S1)
y_candidates.push_back(b_slice);
+ if (s_bit == RTLIL::State::S1 || s_bit == RTLIL::State::Sx)
+ count_maybe_set_s_bits++;
+
if (s_bit == RTLIL::State::S1)
count_set_s_bits++;
}
- if (cell->type == "$safe_pmux" && count_set_s_bits > 1) {
+ if (cell->type == "$safe_pmux" && count_set_s_bits > 1)
y_candidates.clear();
- count_set_s_bits = 0;
- }
- if (count_set_s_bits == 0)
+ if ((cell->type == "$safe_pmux" && count_maybe_set_s_bits > 1) || count_set_s_bits == 0)
y_candidates.push_back(sig_a);
std::vector<RTLIL::Const> y_values;