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authorClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
commitd46bac330520f91ee5bf8027abe98a8f9389f696 (patch)
treed1b87a2409d082fa281d2c9ea100e94c69a43912 /kernel/consteval.h
parent1a88e47396305bd6b5ee2a7a91a1d014ebd37c10 (diff)
Added "$fa" cell type
Diffstat (limited to 'kernel/consteval.h')
-rw-r--r--kernel/consteval.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h
index f995c9cc..7423f950 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -155,6 +155,31 @@ struct ConstEval
else
set(sig_y, y_values.front());
}
+ else if (cell->type == "$fa")
+ {
+ RTLIL::SigSpec sig_c = cell->getPort("\\C");
+ RTLIL::SigSpec sig_x = cell->getPort("\\X");
+ int width = SIZE(sig_c);
+
+ if (!eval(sig_a, undef, cell))
+ return false;
+
+ if (!eval(sig_b, undef, cell))
+ return false;
+
+ if (!eval(sig_c, undef, cell))
+ return false;
+
+ RTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);
+ RTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);
+
+ RTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);
+ RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);
+ RTLIL::Const val_x = const_or(t2, t3, false, false, width);
+
+ set(sig_y, val_y);
+ set(sig_x, val_x);
+ }
else if (cell->type == "$alu")
{
bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();