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authorClifford Wolf <clifford@clifford.at>2014-10-10 16:59:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-10-10 17:07:24 +0200
commit4569a747f8af3880e23408eb93323afc8088b78b (patch)
tree81dcea51020173cd4951e8649f8bd8305e7c2591 /kernel/modtools.h
parentc7f5aab625bb90e766c1852592fdf42c951716c0 (diff)
Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'kernel/modtools.h')
-rw-r--r--kernel/modtools.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/kernel/modtools.h b/kernel/modtools.h
index 58cdd5b0..1b6968d7 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -59,7 +59,7 @@ struct ModIndex : public RTLIL::Monitor
void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
- for (int i = 0; i < SIZE(sig); i++) {
+ for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.insert(PortInfo(cell, port, i));
@@ -68,7 +68,7 @@ struct ModIndex : public RTLIL::Monitor
void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
- for (int i = 0; i < SIZE(sig); i++) {
+ for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.erase(PortInfo(cell, port, i));
@@ -88,7 +88,7 @@ struct ModIndex : public RTLIL::Monitor
database.clear();
for (auto wire : module->wires())
if (wire->port_input || wire->port_output)
- for (int i = 0; i < SIZE(wire); i++) {
+ for (int i = 0; i < GetSize(wire); i++) {
RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));
if (bit.wire && wire->port_input)
database[bit].is_input = true;