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authorClifford Wolf <clifford@clifford.at>2015-02-08 00:01:51 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-08 00:01:51 +0100
commit05d4223fb675ee063ded20cf24eb922c4570634a (patch)
tree482e8b06c23e13bf9719cd9b3748ad1991723579 /kernel/rtlil.cc
parent0da320f151a343fc89f1fc94689f5921ed8fe4ea (diff)
Added SigSpec::has_const()
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b1e2c0e8..776625b9 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1078,6 +1078,7 @@ void RTLIL::Module::check()
for (auto &it : connections_) {
log_assert(it.first.size() == it.second.size());
+ log_assert(!it.first.has_const());
it.first.check();
it.second.check();
}
@@ -2968,6 +2969,17 @@ bool RTLIL::SigSpec::is_fully_undef() const
return true;
}
+bool RTLIL::SigSpec::has_const() const
+{
+ cover("kernel.rtlil.sigspec.has_const");
+
+ pack();
+ for (auto it = chunks_.begin(); it != chunks_.end(); it++)
+ if (it->width > 0 && it->wire == NULL)
+ return true;
+ return false;
+}
+
bool RTLIL::SigSpec::has_marked_bits() const
{
cover("kernel.rtlil.sigspec.has_marked_bits");