diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-06-02 17:53:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-02 17:53:30 +0200 |
| commit | 21d9251e52c2a1807306fd4067de0750e45465c0 (patch) | |
| tree | 7e70e27d4acdbeddb2b30875acaad517274ad3bc /kernel/rtlil.cc | |
| parent | 5f2c5f90178dbd5b26956d60881cab132a5982bd (diff) | |
Added "dump" command (part ilang backend)
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b0dcfe42..2c255285 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -101,7 +101,7 @@ std::string RTLIL::Const::as_string() const return ret; } -bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) +bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const { if (full_selection) return true; @@ -112,7 +112,7 @@ bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) return false; } -bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) +bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const { if (full_selection) return true; @@ -121,14 +121,14 @@ bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) return false; } -bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) +bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const { if (full_selection) return true; if (selected_modules.count(mod_name) > 0) return true; if (selected_members.count(mod_name) > 0) - if (selected_members[mod_name].count(memb_name) > 0) + if (selected_members.at(mod_name).count(memb_name) > 0) return true; return false; } @@ -217,7 +217,7 @@ void RTLIL::Design::optimize() it.second.optimize(this); } -bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) +bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const { if (!selected_active_module.empty() && mod_name != selected_active_module) return false; @@ -226,7 +226,7 @@ bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) return selection_stack.back().selected_module(mod_name); } -bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) +bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const { if (!selected_active_module.empty() && mod_name != selected_active_module) return false; @@ -235,7 +235,7 @@ bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) return selection_stack.back().selected_whole_module(mod_name); } -bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) +bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const { if (!selected_active_module.empty() && mod_name != selected_active_module) return false; |