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authorClifford Wolf <clifford@clifford.at>2014-08-15 14:18:40 +0200
committerClifford Wolf <clifford@clifford.at>2014-08-15 14:18:40 +0200
commitb64b38eea2e9a7de30d6045f069c86bf4446134f (patch)
tree1792429b244f7af0b4ed33f8e57c1e591c8efd02 /kernel/rtlil.cc
parentf092b5014895dc5dc62b8103fcedf94cfa9f85a8 (diff)
Renamed $lut ports to follow A-Y naming scheme
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 614ea770..d118b625 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -615,8 +615,8 @@ namespace {
if (cell->type == "$lut") {
param("\\LUT");
- port("\\I", param("\\WIDTH"));
- port("\\O", 1);
+ port("\\A", param("\\WIDTH"));
+ port("\\Y", 1);
check_expected();
return;
}
@@ -1388,8 +1388,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
RTLIL::Cell *cell = addCell(name, "$lut");
cell->parameters["\\LUT"] = lut;
cell->parameters["\\WIDTH"] = sig_i.size();
- cell->setPort("\\I", sig_i);
- cell->setPort("\\O", sig_o);
+ cell->setPort("\\A", sig_i);
+ cell->setPort("\\Y", sig_o);
return cell;
}