diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-09-01 11:36:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-01 11:36:02 +0200 |
| commit | e07698818dfe3c8e5f87b13090c7e70d22189e2a (patch) | |
| tree | eb4384ce1b2ef627f8fe0a9533c298e308c8337d /kernel/rtlil.h | |
| parent | e3664066d5684af444c5a1edb02b9e7543cba38d (diff) | |
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 93532938..b8733c4e 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -864,7 +864,7 @@ public: struct RTLIL::SigChunk { RTLIL::Wire *wire; - RTLIL::Const data; // only used if wire == NULL, LSB at index 0 + std::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0 int width, offset; SigChunk(); @@ -895,8 +895,8 @@ struct RTLIL::SigBit SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); } - SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; } - SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; } + SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } + SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } SigBit(const RTLIL::SigSpec &sig); bool operator <(const RTLIL::SigBit &other) const { |