Renamed RTLIL::{Module,Cell}::connections to connections_

6 files changed, 211 insertions, 190 deletions

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 7b1b798c..5469fa80 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -43,7 +43,7 @@ struct ConstEval
 		for (auto &it : module->cells) {
 			if (!ct.cell_known(it.second->type))
 				continue;
-			for (auto &it2 : it.second->connections)
+			for (auto &it2 : it.second->connections_)
 				if (ct.cell_output(it.second->type, it2.first))
 					sig2driver.insert(assign_map(it2.second), it.second);
 		}
@@ -87,22 +87,22 @@ struct ConstEval
 	{
 		RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-		assert(cell->connections.count("\\Y") > 0);
-		sig_y = values_map(assign_map(cell->connections["\\Y"]));
+		assert(cell->connections_.count("\\Y") > 0);
+		sig_y = values_map(assign_map(cell->connections_["\\Y"]));
 		if (sig_y.is_fully_const())
 			return true;
 
-		if (cell->connections.count("\\S") > 0) {
-			sig_s = cell->connections["\\S"];
+		if (cell->connections_.count("\\S") > 0) {
+			sig_s = cell->connections_["\\S"];
 			if (!eval(sig_s, undef, cell))
 				return false;
 		}
 
-		if (cell->connections.count("\\A") > 0)
-			sig_a = cell->connections["\\A"];
+		if (cell->connections_.count("\\A") > 0)
+			sig_a = cell->connections_["\\A"];
 
-		if (cell->connections.count("\\B") > 0)
-			sig_b = cell->connections["\\B"];
+		if (cell->connections_.count("\\B") > 0)
+			sig_b = cell->connections_["\\B"];
 
 		if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
 		{
diff --git a/kernel/modwalker.h b/kernel/modwalker.h
index 6c3da5dd..efd97379 100644
--- a/kernel/modwalker.h
+++ b/kernel/modwalker.h
@@ -88,12 +88,12 @@ struct ModWalker
 	void add_cell(RTLIL::Cell *cell)
 	{
 		if (ct.cell_known(cell->type)) {
-			for (auto &conn : cell->connections)
+			for (auto &conn : cell->connections_)
 				add_cell_port(cell, conn.first, sigmap(conn.second),
 						ct.cell_output(cell->type, conn.first),
 						ct.cell_input(cell->type, conn.first));
 		} else {
-			for (auto &conn : cell->connections)
+			for (auto &conn : cell->connections_)
 				add_cell_port(cell, conn.first, sigmap(conn.second), true, true);
 		}
 	}
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1a6e386f..4d0aadbb 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -348,9 +348,9 @@ namespace {
 
 		void port(const char *name, int width)
 		{
-			if (cell->connections.count(name) == 0)
+			if (cell->connections_.count(name) == 0)
 				error(__LINE__);
-			if (cell->connections.at(name).size() != width)
+			if (cell->connections_.at(name).size() != width)
 				error(__LINE__);
 			expected_ports.insert(name);
 		}
@@ -360,7 +360,7 @@ namespace {
 			for (auto &para : cell->parameters)
 				if (expected_params.count(para.first) == 0)
 					error(__LINE__);
-			for (auto &conn : cell->connections)
+			for (auto &conn : cell->connections_)
 				if (expected_ports.count(conn.first) == 0)
 					error(__LINE__);
 
@@ -379,13 +379,13 @@ namespace {
 
 			for (const char *p = ports; *p; p++) {
 				char portname[3] = { '\\', *p, 0 };
-				if (cell->connections.count(portname) == 0)
+				if (cell->connections_.count(portname) == 0)
 					error(__LINE__);
-				if (cell->connections.at(portname).size() != 1)
+				if (cell->connections_.at(portname).size() != 1)
 					error(__LINE__);
 			}
 
-			for (auto &conn : cell->connections) {
+			for (auto &conn : cell->connections_) {
 				if (conn.first.size() != 2 || conn.first.at(0) != '\\')
 					error(__LINE__);
 				if (strchr(ports, conn.first.at(1)) == NULL)
@@ -734,7 +734,7 @@ void RTLIL::Module::check()
 		assert(it.first == it.second->name);
 		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
-		for (auto &it2 : it.second->connections) {
+		for (auto &it2 : it.second->connections_) {
 			assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 			it2.second.check();
 		}
@@ -754,7 +754,7 @@ void RTLIL::Module::check()
 		// FIXME: More checks here..
 	}
 
-	for (auto &it : connections) {
+	for (auto &it : connections_) {
 		assert(it.first.size() == it.second.size());
 		it.first.check();
 		it.second.check();
@@ -773,7 +773,7 @@ void RTLIL::Module::optimize()
 void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
 {
 	new_mod->name = name;
-	new_mod->connections = connections;
+	new_mod->connections_ = connections_;
 	new_mod->attributes = attributes;
 
 	for (auto &it : wires)
@@ -873,6 +873,11 @@ static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 	return a->port_id < b->port_id;
 }
 
+void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs)
+{
+	connections_.push_back(RTLIL::SigSig(lhs, rhs));
+}
+
 void RTLIL::Module::fixup_ports()
 {
 	std::vector<RTLIL::Wire*> all_ports;
@@ -909,7 +914,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type)
 RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *other)
 {
 	RTLIL::Cell *cell = addCell(name, other->type);
-	cell->connections = other->connections;
+	cell->connections_ = other->connections_;
 	cell->parameters = other->parameters;
 	cell->attributes = other->attributes;
 	return cell;
@@ -923,8 +928,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 		cell->parameters["\\A_SIGNED"] = is_signed;         \
 		cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
-		cell->connections["\\A"] = sig_a;                   \
-		cell->connections["\\Y"] = sig_y;                   \
+		cell->connections_["\\A"] = sig_a;                   \
+		cell->connections_["\\Y"] = sig_y;                   \
 		add(cell);                                          \
 		return cell;                                        \
 	} \
@@ -955,9 +960,9 @@ DEF_METHOD(LogicNot,   1, "$logic_not")
 		cell->parameters["\\A_WIDTH"] = sig_a.size();        \
 		cell->parameters["\\B_WIDTH"] = sig_b.size();        \
 		cell->parameters["\\Y_WIDTH"] = sig_y.size();        \
-		cell->connections["\\A"] = sig_a;                   \
-		cell->connections["\\B"] = sig_b;                   \
-		cell->connections["\\Y"] = sig_y;                   \
+		cell->connections_["\\A"] = sig_a;                   \
+		cell->connections_["\\B"] = sig_b;                   \
+		cell->connections_["\\Y"] = sig_y;                   \
 		add(cell);                                          \
 		return cell;                                        \
 	} \
@@ -999,10 +1004,10 @@ DEF_METHOD(LogicOr,  1, "$logic_or")
 		cell->parameters["\\WIDTH"] = sig_a.size();               \
 		cell->parameters["\\WIDTH"] = sig_b.size();               \
 		if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size();  \
-		cell->connections["\\A"] = sig_a;                        \
-		cell->connections["\\B"] = sig_b;                        \
-		cell->connections["\\S"] = sig_s;                        \
-		cell->connections["\\Y"] = sig_y;                        \
+		cell->connections_["\\A"] = sig_a;                        \
+		cell->connections_["\\B"] = sig_b;                        \
+		cell->connections_["\\S"] = sig_s;                        \
+		cell->connections_["\\Y"] = sig_y;                        \
 		add(cell);                                               \
 		return cell;                                             \
 	} \
@@ -1021,8 +1026,8 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections["\\" #_P1] = sig1;        \
-		cell->connections["\\" #_P2] = sig2;        \
+		cell->connections_["\\" #_P1] = sig1;        \
+		cell->connections_["\\" #_P2] = sig2;        \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1036,9 +1041,9 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections["\\" #_P1] = sig1;        \
-		cell->connections["\\" #_P2] = sig2;        \
-		cell->connections["\\" #_P3] = sig3;        \
+		cell->connections_["\\" #_P1] = sig1;        \
+		cell->connections_["\\" #_P2] = sig2;        \
+		cell->connections_["\\" #_P3] = sig3;        \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1052,10 +1057,10 @@ DEF_METHOD(SafePmux, "$safe_pmux",  1)
 		RTLIL::Cell *cell = new RTLIL::Cell;        \
 		cell->name = name;                          \
 		cell->type = _type;                         \
-		cell->connections["\\" #_P1] = sig1;        \
-		cell->connections["\\" #_P2] = sig2;        \
-		cell->connections["\\" #_P3] = sig3;        \
-		cell->connections["\\" #_P4] = sig4;        \
+		cell->connections_["\\" #_P1] = sig1;        \
+		cell->connections_["\\" #_P2] = sig2;        \
+		cell->connections_["\\" #_P3] = sig3;        \
+		cell->connections_["\\" #_P4] = sig4;        \
 		add(cell);                                  \
 		return cell;                                \
 	} \
@@ -1083,9 +1088,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\B_WIDTH"] = sig_b.size();
 	cell->parameters["\\Y_WIDTH"] = sig_y.size();
-	cell->connections["\\A"] = sig_a;
-	cell->connections["\\B"] = sig_b;
-	cell->connections["\\Y"] = sig_y;
+	cell->connections_["\\A"] = sig_a;
+	cell->connections_["\\B"] = sig_b;
+	cell->connections_["\\Y"] = sig_y;
 	add(cell);
 	return cell;
 }
@@ -1098,8 +1103,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a,
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\Y_WIDTH"] = sig_y.size();
 	cell->parameters["\\OFFSET"] = offset;
-	cell->connections["\\A"] = sig_a;
-	cell->connections["\\Y"] = sig_y;
+	cell->connections_["\\A"] = sig_a;
+	cell->connections_["\\Y"] = sig_y;
 	add(cell);
 	return cell;
 }
@@ -1111,9 +1116,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	cell->type = "$concat";
 	cell->parameters["\\A_WIDTH"] = sig_a.size();
 	cell->parameters["\\B_WIDTH"] = sig_b.size();
-	cell->connections["\\A"] = sig_a;
-	cell->connections["\\B"] = sig_b;
-	cell->connections["\\Y"] = sig_y;
+	cell->connections_["\\A"] = sig_a;
+	cell->connections_["\\B"] = sig_b;
+	cell->connections_["\\Y"] = sig_y;
 	add(cell);
 	return cell;
 }
@@ -1125,8 +1130,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
 	cell->type = "$lut";
 	cell->parameters["\\LUT"] = lut;
 	cell->parameters["\\WIDTH"] = sig_i.size();
-	cell->connections["\\I"] = sig_i;
-	cell->connections["\\O"] = sig_o;
+	cell->connections_["\\I"] = sig_i;
+	cell->connections_["\\O"] = sig_o;
 	add(cell);
 	return cell;
 }
@@ -1136,8 +1141,8 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = "$assert";
-	cell->connections["\\A"] = sig_a;
-	cell->connections["\\EN"] = sig_en;
+	cell->connections_["\\A"] = sig_a;
+	cell->connections_["\\EN"] = sig_en;
 	add(cell);
 	return cell;
 }
@@ -1150,9 +1155,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set,
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections["\\SET"] = sig_set;
-	cell->connections["\\CLR"] = sig_clr;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\SET"] = sig_set;
+	cell->connections_["\\CLR"] = sig_clr;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1164,9 +1169,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk,
 	cell->type = "$dff";
 	cell->parameters["\\CLK_POLARITY"] = clk_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections["\\CLK"] = sig_clk;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\CLK"] = sig_clk;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1181,11 +1186,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections["\\CLK"] = sig_clk;
-	cell->connections["\\SET"] = sig_set;
-	cell->connections["\\CLR"] = sig_clr;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\CLK"] = sig_clk;
+	cell->connections_["\\SET"] = sig_set;
+	cell->connections_["\\CLR"] = sig_clr;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1200,10 +1205,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
 	cell->parameters["\\ARST_POLARITY"] = arst_polarity;
 	cell->parameters["\\ARST_VALUE"] = arst_value;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections["\\CLK"] = sig_clk;
-	cell->connections["\\ARST"] = sig_arst;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\CLK"] = sig_clk;
+	cell->connections_["\\ARST"] = sig_arst;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1215,9 +1220,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e
 	cell->type = "$dlatch";
 	cell->parameters["\\EN_POLARITY"] = en_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections["\\EN"] = sig_en;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\EN"] = sig_en;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1232,11 +1237,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig
 	cell->parameters["\\SET_POLARITY"] = set_polarity;
 	cell->parameters["\\CLR_POLARITY"] = clr_polarity;
 	cell->parameters["\\WIDTH"] = sig_q.size();
-	cell->connections["\\EN"] = sig_en;
-	cell->connections["\\SET"] = sig_set;
-	cell->connections["\\CLR"] = sig_clr;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\EN"] = sig_en;
+	cell->connections_["\\SET"] = sig_set;
+	cell->connections_["\\CLR"] = sig_clr;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1246,9 +1251,9 @@ RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
-	cell->connections["\\C"] = sig_clk;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\C"] = sig_clk;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1259,11 +1264,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
-	cell->connections["\\C"] = sig_clk;
-	cell->connections["\\S"] = sig_set;
-	cell->connections["\\R"] = sig_clr;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\C"] = sig_clk;
+	cell->connections_["\\S"] = sig_set;
+	cell->connections_["\\R"] = sig_clr;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1274,10 +1279,10 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0');
-	cell->connections["\\C"] = sig_clk;
-	cell->connections["\\R"] = sig_arst;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\C"] = sig_clk;
+	cell->connections_["\\R"] = sig_arst;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1287,9 +1292,9 @@ RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec s
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N');
-	cell->connections["\\E"] = sig_en;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\E"] = sig_en;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
@@ -1300,11 +1305,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
 	RTLIL::Cell *cell = new RTLIL::Cell;
 	cell->name = name;
 	cell->type = stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N');
-	cell->connections["\\E"] = sig_en;
-	cell->connections["\\S"] = sig_set;
-	cell->connections["\\R"] = sig_clr;
-	cell->connections["\\D"] = sig_d;
-	cell->connections["\\Q"] = sig_q;
+	cell->connections_["\\E"] = sig_en;
+	cell->connections_["\\S"] = sig_set;
+	cell->connections_["\\R"] = sig_clr;
+	cell->connections_["\\D"] = sig_d;
+	cell->connections_["\\Q"] = sig_q;
 	add(cell);
 	return cell;
 }
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index fbd6e719..96bda753 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -279,13 +279,16 @@ struct RTLIL::Module
 	std::map<RTLIL::IdString, RTLIL::Memory*> memories;
 	std::map<RTLIL::IdString, RTLIL::Cell*> cells;
 	std::map<RTLIL::IdString, RTLIL::Process*> processes;
-	std::vector<RTLIL::SigSig> connections;
+	std::vector<RTLIL::SigSig> connections_;
 	RTLIL_ATTRIBUTE_MEMBERS
+
 	virtual ~Module();
 	virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
 	virtual size_t count_id(RTLIL::IdString id);
 	virtual void check();
 	virtual void optimize();
+
+	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
 	void fixup_ports();
 
 	template<typename T> void rewrite_sigspecs(T functor);
@@ -435,37 +438,50 @@ struct RTLIL::Module
 	RTLIL::SigSpec MuxGate  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s);
 };
 
-struct RTLIL::Wire {
+struct RTLIL::Wire
+{
+//protected:
+	// use module->addWire() and module->remove() to create or destroy wires
+	friend struct RTLIL::Module;
+	Wire();
+	~Wire() { };
+
+public:
+	// do not simply copy wires
+	//Wire(RTLIL::Wire &other) = delete;
+	//void operator=(RTLIL::Wire &other) = delete;
+
 	RTLIL::IdString name;
 	int width, start_offset, port_id;
 	bool port_input, port_output;
 	RTLIL_ATTRIBUTE_MEMBERS
-	Wire();
 };
 
-struct RTLIL::Memory {
+struct RTLIL::Memory
+{
+	Memory();
+
 	RTLIL::IdString name;
 	int width, start_offset, size;
 	RTLIL_ATTRIBUTE_MEMBERS
-	Memory();
 };
 
 struct RTLIL::Cell
 {
 protected:
-	// Use module->addCell() and module->remove() to create or destroy modules.
+	// use module->addCell() and module->remove() to create or destroy cells
 	friend struct RTLIL::Module;
 	Cell() { };
 	~Cell() { };
 
 public:
-	// do not copy simply cells
+	// do not simply copy cells
 	Cell(RTLIL::Cell &other) = delete;
 	void operator=(RTLIL::Cell &other) = delete;
 
 	RTLIL::IdString name;
 	RTLIL::IdString type;
-	std::map<RTLIL::IdString, RTLIL::SigSpec> connections;
+	std::map<RTLIL::IdString, RTLIL::SigSpec> connections_;
 	std::map<RTLIL::IdString, RTLIL::Const> parameters;
 	RTLIL_ATTRIBUTE_MEMBERS
 	void check();
@@ -686,7 +702,7 @@ void RTLIL::Module::rewrite_sigspecs(T functor)
 		it.second->rewrite_sigspecs(functor);
 	for (auto &it : processes)
 		it.second->rewrite_sigspecs(functor);
-	for (auto &it : connections) {
+	for (auto &it : connections_) {
 		functor(it.first);
 		functor(it.second);
 	}
@@ -694,7 +710,7 @@ void RTLIL::Module::rewrite_sigspecs(T functor)
 
 template<typename T>
 void RTLIL::Cell::rewrite_sigspecs(T functor) {
-	for (auto &it : connections)
+	for (auto &it : connections_)
 		functor(it.second);
 }
 
diff --git a/kernel/satgen.h b/kernel/satgen.h
index ea04cb40..ec4480c3 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -182,9 +182,9 @@ struct SatGen
 
 		if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare))
 		{
-			std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 			if (is_arith_compare)
 				extendSignalWidth(undef_a, undef_b, cell, true);
 			else
@@ -195,7 +195,7 @@ struct SatGen
 			int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
 
 			if (cell->type == "$div" || cell->type == "$mod") {
-				std::vector<int> b = importSigSpec(cell->connections.at("\\B"), timestep);
+				std::vector<int> b = importSigSpec(cell->connections_.at("\\B"), timestep);
 				undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
 			}
 
@@ -215,9 +215,9 @@ struct SatGen
 				cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
 				cell->type == "$add" || cell->type == "$sub")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -237,9 +237,9 @@ struct SatGen
 
 			if (model_undef && !arith_undef_handled)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
 
 				if (cell->type == "$and" || cell->type == "$_AND_") {
@@ -265,7 +265,7 @@ struct SatGen
 			}
 			else if (model_undef)
 			{
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -273,16 +273,16 @@ struct SatGen
 
 		if (cell->type == "$_INV_" || cell->type == "$not")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(ez->vec_not(a), yy));
 
 			if (model_undef) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, true);
 				ez->assume(ez->vec_eq(undef_a, undef_y));
 				undefGating(y, yy, undef_y);
@@ -292,20 +292,20 @@ struct SatGen
 
 		if (cell->type == "$_MUX_" || cell->type == "$mux")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> s = importDefSigSpec(cell->connections.at("\\S"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> s = importDefSigSpec(cell->connections_.at("\\S"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-				std::vector<int> undef_s = importUndefSigSpec(cell->connections.at("\\S"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 				std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
 				std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
@@ -318,10 +318,10 @@ struct SatGen
 
 		if (cell->type == "$pmux" || cell->type == "$safe_pmux")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> s = importDefSigSpec(cell->connections.at("\\S"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> s = importDefSigSpec(cell->connections_.at("\\S"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -336,10 +336,10 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-				std::vector<int> undef_s = importUndefSigSpec(cell->connections.at("\\S"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_s = importUndefSigSpec(cell->connections_.at("\\S"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 				int maybe_one_hot = ez->FALSE;
 				int maybe_many_hot = ez->FALSE;
@@ -387,8 +387,8 @@ struct SatGen
 
 		if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -402,8 +402,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0");
 
 				if (cell->type == "$pos" || cell->type == "$bu0") {
@@ -422,8 +422,8 @@ struct SatGen
 		if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
 				cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -442,8 +442,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				int aX = ez->expression(ezSAT::OpOr, undef_a);
 
 				if (cell->type == "$reduce_and") {
@@ -469,12 +469,12 @@ struct SatGen
 
 		if (cell->type == "$logic_and" || cell->type == "$logic_or")
 		{
-			std::vector<int> vec_a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> vec_b = importDefSigSpec(cell->connections.at("\\B"), timestep);
+			std::vector<int> vec_a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> vec_b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
 
 			int a = ez->expression(ez->OpOr, vec_a);
 			int b = ez->expression(ez->OpOr, vec_b);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -487,9 +487,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 				int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
 				int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
@@ -516,16 +516,16 @@ struct SatGen
 		if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt")
 		{
 			bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 			extendSignalWidth(a, b, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
 			if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 				a = ez->vec_or(a, undef_a);
 				b = ez->vec_or(b, undef_b);
@@ -548,9 +548,9 @@ struct SatGen
 
 			if (model_undef && (cell->type == "$eqx" || cell->type == "$nex"))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				if (cell->type == "$eqx")
@@ -565,9 +565,9 @@ struct SatGen
 			}
 			else if (model_undef && (cell->type == "$eq" || cell->type == "$ne"))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@@ -589,7 +589,7 @@ struct SatGen
 			else
 			{
 				if (model_undef) {
-					std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+					std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 					undefGating(y, yy, undef_y);
 				}
 				log_assert(!model_undef || arith_undef_handled);
@@ -599,9 +599,9 @@ struct SatGen
 
 		if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 			char shift_left = cell->type == "$shl" || cell->type == "$sshl";
 			bool sign_extend = cell->type == "$sshr" && cell->parameters["\\A_SIGNED"].as_bool();
@@ -627,9 +627,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->connections_.at("\\A"), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->connections_.at("\\B"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 
 				while (undef_y.size() < undef_a.size())
 					undef_y.push_back(ez->literal());
@@ -657,9 +657,9 @@ struct SatGen
 
 		if (cell->type == "$mul")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -676,7 +676,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -684,9 +684,9 @@ struct SatGen
 
 		if (cell->type == "$div" || cell->type == "$mod")
 		{
-			std::vector<int> a = importDefSigSpec(cell->connections.at("\\A"), timestep);
-			std::vector<int> b = importDefSigSpec(cell->connections.at("\\B"), timestep);
-			std::vector<int> y = importDefSigSpec(cell->connections.at("\\Y"), timestep);
+			std::vector<int> a = importDefSigSpec(cell->connections_.at("\\A"), timestep);
+			std::vector<int> b = importDefSigSpec(cell->connections_.at("\\B"), timestep);
+			std::vector<int> y = importDefSigSpec(cell->connections_.at("\\Y"), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -740,11 +740,11 @@ struct SatGen
 						only_first_one.at(0) = ez->TRUE;
 						div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
 					} else {
-						div_zero_result.insert(div_zero_result.end(), cell->connections.at("\\A").size(), ez->TRUE);
+						div_zero_result.insert(div_zero_result.end(), cell->connections_.at("\\A").size(), ez->TRUE);
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
 					}
 				} else {
-					int copy_a_bits = std::min(cell->connections.at("\\A").size(), cell->connections.at("\\B").size());
+					int copy_a_bits = std::min(cell->connections_.at("\\A").size(), cell->connections_.at("\\B").size());
 					div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
 					if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@@ -756,7 +756,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->connections_.at("\\Y"), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -764,17 +764,17 @@ struct SatGen
 
 		if (cell->type == "$slice")
 		{
-			RTLIL::SigSpec a = cell->connections.at("\\A");
-			RTLIL::SigSpec y = cell->connections.at("\\Y");
+			RTLIL::SigSpec a = cell->connections_.at("\\A");
+			RTLIL::SigSpec y = cell->connections_.at("\\Y");
 			ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
 			return true;
 		}
 
 		if (cell->type == "$concat")
 		{
-			RTLIL::SigSpec a = cell->connections.at("\\A");
-			RTLIL::SigSpec b = cell->connections.at("\\B");
-			RTLIL::SigSpec y = cell->connections.at("\\Y");
+			RTLIL::SigSpec a = cell->connections_.at("\\A");
+			RTLIL::SigSpec b = cell->connections_.at("\\B");
+			RTLIL::SigSpec y = cell->connections_.at("\\Y");
 
 			RTLIL::SigSpec ab = a;
 			ab.append(b);
@@ -787,20 +787,20 @@ struct SatGen
 		{
 			if (timestep == 1)
 			{
-				initial_state.add((*sigmap)(cell->connections.at("\\Q")));
+				initial_state.add((*sigmap)(cell->connections_.at("\\Q")));
 			}
 			else
 			{
-				std::vector<int> d = importDefSigSpec(cell->connections.at("\\D"), timestep-1);
-				std::vector<int> q = importDefSigSpec(cell->connections.at("\\Q"), timestep);
+				std::vector<int> d = importDefSigSpec(cell->connections_.at("\\D"), timestep-1);
+				std::vector<int> q = importDefSigSpec(cell->connections_.at("\\Q"), timestep);
 
 				std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
 				ez->assume(ez->vec_eq(d, qq));
 
 				if (model_undef)
 				{
-					std::vector<int> undef_d = importUndefSigSpec(cell->connections.at("\\D"), timestep-1);
-					std::vector<int> undef_q = importUndefSigSpec(cell->connections.at("\\Q"), timestep);
+					std::vector<int> undef_d = importUndefSigSpec(cell->connections_.at("\\D"), timestep-1);
+					std::vector<int> undef_q = importUndefSigSpec(cell->connections_.at("\\Q"), timestep);
 
 					ez->assume(ez->vec_eq(undef_d, undef_q));
 					undefGating(q, qq, undef_q);
@@ -812,8 +812,8 @@ struct SatGen
 		if (cell->type == "$assert")
 		{
 			std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
-			asserts_a[pf].append((*sigmap)(cell->connections.at("\\A")));
-			asserts_en[pf].append((*sigmap)(cell->connections.at("\\EN")));
+			asserts_a[pf].append((*sigmap)(cell->connections_.at("\\A")));
+			asserts_en[pf].append((*sigmap)(cell->connections_.at("\\EN")));
 			return true;
 		}
 
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 1a84194e..ea95e06e 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -269,7 +269,7 @@ struct SigMap
 	void set(RTLIL::Module *module)
 	{
 		clear();
-		for (auto &it : module->connections)
+		for (auto &it : module->connections_)
 			add(it.first, it.second);
 	}