No implicit conversion from IdString to anything else

4 files changed, 22 insertions, 22 deletions

diff --git a/kernel/log.cc b/kernel/log.cc
index 01f6207e..81cc26da 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -215,7 +215,7 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
 
 const char *log_id(RTLIL::IdString str)
 {
-	const char *p = str;
+	const char *p = str.c_str();
 	log_assert(RTLIL::IdString::global_refcount_storage_[str.index_] > 1);
 	if (p[0] == '\\' && p[1] != '$' && p[1] != 0)
 		return p+1;
diff --git a/kernel/register.cc b/kernel/register.cc
index 4d204069..868dbb94 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -240,7 +240,7 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
 void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command)
 {
 	std::string backup_selected_active_module = design->selected_active_module;
-	design->selected_active_module = module->name;
+	design->selected_active_module = module->name.str();
 	design->selection_stack.push_back(RTLIL::Selection(false));
 	design->selection_stack.back().select(module);
 
@@ -253,7 +253,7 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
 void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args)
 {
 	std::string backup_selected_active_module = design->selected_active_module;
-	design->selected_active_module = module->name;
+	design->selected_active_module = module->name.str();
 	design->selection_stack.push_back(RTLIL::Selection(false));
 	design->selection_stack.back().select(module);
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9ee8123f..2838449b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -286,7 +286,7 @@ void RTLIL::Design::check()
 	for (auto &it : modules_) {
 		log_assert(this == it.second->design);
 		log_assert(it.first == it.second->name);
-		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(!it.first.empty());
 		it.second->check();
 	}
 #endif
@@ -499,7 +499,7 @@ namespace {
 
 		void check()
 		{
-			if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
+			if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
 					cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
 				return;
 
@@ -818,38 +818,38 @@ void RTLIL::Module::check()
 	for (auto &it : wires_) {
 		log_assert(this == it.second->module);
 		log_assert(it.first == it.second->name);
-		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(!it.first.empty());
 		log_assert(it.second->width >= 0);
 		log_assert(it.second->port_id >= 0);
 		for (auto &it2 : it.second->attributes) {
-			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(!it2.first.empty());
 		}
 	}
 
 	for (auto &it : memories) {
 		log_assert(it.first == it.second->name);
-		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(!it.first.empty());
 		log_assert(it.second->width >= 0);
 		log_assert(it.second->size >= 0);
 		for (auto &it2 : it.second->attributes) {
-			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(!it2.first.empty());
 		}
 	}
 
 	for (auto &it : cells_) {
 		log_assert(this == it.second->module);
 		log_assert(it.first == it.second->name);
-		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
-		log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
+		log_assert(!it.first.empty());
+		log_assert(!it.second->type.empty());
 		for (auto &it2 : it.second->connections()) {
-			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(!it2.first.empty());
 			it2.second.check();
 		}
 		for (auto &it2 : it.second->attributes) {
-			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(!it2.first.empty());
 		}
 		for (auto &it2 : it.second->parameters) {
-			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(!it2.first.empty());
 		}
 		InternalCellChecker checker(this, it.second);
 		checker.check();
@@ -857,7 +857,7 @@ void RTLIL::Module::check()
 
 	for (auto &it : processes) {
 		log_assert(it.first == it.second->name);
-		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(!it.first.empty());
 		// FIXME: More checks here..
 	}
 
@@ -868,7 +868,7 @@ void RTLIL::Module::check()
 	}
 
 	for (auto &it : attributes) {
-		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(!it.first.empty());
 	}
 #endif
 }
@@ -1597,7 +1597,7 @@ void RTLIL::Cell::check()
 
 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 {
-	if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
+	if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
 			type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
 		return;
 
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6529603e..502969a1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -162,11 +162,7 @@ namespace RTLIL
 			*this = id;
 		}
 
-		const char*c_str() const {
-			return global_id_storage_.at(index_);
-		}
-
-		operator const char*() const {
+		const char *c_str() const {
 			return global_id_storage_.at(index_);
 		}
 
@@ -193,6 +189,10 @@ namespace RTLIL
 			return c_str()[i];
 		}
 
+		char operator[](size_t i) const {
+			return c_str()[i];
+		}
+
 		std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
 			if (len == std::string::npos || len >= strlen(c_str() + pos))
 				return std::string(c_str() + pos);