diff options
author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
commit | 7f110e7018d35f29cf6a5d3031400a8044c8d32d (patch) | |
tree | 9c65e6929e43faec716efab17b37bd53f9afa4b3 /kernel | |
parent | 6af80769678f260aa4aeaf3b12b54dfdc15fa5dd (diff) |
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.cc | 23 | ||||
-rw-r--r-- | kernel/rtlil.h | 3 |
2 files changed, 13 insertions, 13 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 6f150c1e..5f056f89 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3197,6 +3197,17 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const return chunks_[0]; } +RTLIL::SigBit RTLIL::SigSpec::as_bit() const +{ + cover("kernel.rtlil.sigspec.as_bit"); + + log_assert(width_ == 1); + if (packed()) + return RTLIL::SigBit(*chunks_.begin()); + else + return bits_[0]; +} + bool RTLIL::SigSpec::match(std::string pattern) const { cover("kernel.rtlil.sigspec.match"); @@ -3284,18 +3295,6 @@ dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::S return new_map; } -RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const -{ - cover("kernel.rtlil.sigspec.to_single_sigbit"); - - pack(); - log_assert(width_ == 1); - for (auto &c : chunks_) - if (c.width) - return RTLIL::SigBit(c); - log_abort(); -} - static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep) { size_t start = 0, end = 0; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 43ef5806..99dcb311 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -690,6 +690,7 @@ public: bool is_wire() const; bool is_chunk() const; + inline bool is_bit() const { return width_ == 1; } bool is_fully_const() const; bool is_fully_zero() const; @@ -704,6 +705,7 @@ public: RTLIL::Const as_const() const; RTLIL::Wire *as_wire() const; RTLIL::SigChunk as_chunk() const; + RTLIL::SigBit as_bit() const; bool match(std::string pattern) const; @@ -712,7 +714,6 @@ public: std::vector<RTLIL::SigBit> to_sigbit_vector() const; std::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const; dict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const; - RTLIL::SigBit to_single_sigbit() const; static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); |