Added global yosys_celltypes

2 files changed, 66 insertions, 40 deletions

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 32e14419..3a56de2f 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -96,88 +96,102 @@ struct CellTypes
 			"$logic_and", "$logic_or", "$concat", "$macc"
 		};
 
+		IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y";
+		IdString P = "\\P", G = "\\G", C = "\\C", X = "\\X";
+		IdString BI = "\\BI", CI = "\\CI", CO = "\\CO", EN = "\\EN";
+
 		for (auto type : unary_ops)
-			setup_type(type, {"\\A"}, {"\\Y"}, true);
+			setup_type(type, {A}, {Y}, true);
 
 		for (auto type : binary_ops)
-			setup_type(type, {"\\A", "\\B"}, {"\\Y"}, true);
+			setup_type(type, {A, B}, {Y}, true);
 
 		for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"}))
-			setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, true);
+			setup_type(type, {A, B, S}, {Y}, true);
 
-		setup_type("$lcu", {"\\P", "\\G", "\\CI"}, {"\\CO"}, true);
-		setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true);
-		setup_type("$fa", {"\\A", "\\B", "\\C"}, {"\\X", "\\Y"}, true);
+		setup_type("$lcu", {P, G, CI}, {CO}, true);
+		setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
+		setup_type("$fa", {A, B, C}, {X, Y}, true);
 
-		setup_type("$assert", {"\\A", "\\EN"}, pool<RTLIL::IdString>(), true);
+		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
 	}
 
 	void setup_internals_mem()
 	{
-		setup_type("$sr", {"\\SET", "\\CLR"}, {"\\Q"});
-		setup_type("$dff", {"\\CLK", "\\D"}, {"\\Q"});
-		setup_type("$dffe", {"\\CLK", "\\EN", "\\D"}, {"\\Q"});
-		setup_type("$dffsr", {"\\CLK", "\\SET", "\\CLR", "\\D"}, {"\\Q"});
-		setup_type("$adff", {"\\CLK", "\\ARST", "\\D"}, {"\\Q"});
-		setup_type("$dlatch", {"\\EN", "\\D"}, {"\\Q"});
-		setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"});
-
-		setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"});
-		setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, pool<RTLIL::IdString>());
-		setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"});
-
-		setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"});
+		IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
+		IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA";
+		IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
+		IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
+		IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";
+
+		setup_type("$sr", {SET, CLR}, {Q});
+		setup_type("$dff", {CLK, D}, {Q});
+		setup_type("$dffe", {CLK, EN, D}, {Q});
+		setup_type("$dffsr", {CLK, SET, CLR, D}, {Q});
+		setup_type("$adff", {CLK, ARST, D}, {Q});
+		setup_type("$dlatch", {EN, D}, {Q});
+		setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q});
+
+		setup_type("$memrd", {CLK, ADDR}, {DATA});
+		setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
+		setup_type("$mem", {RD_CLK, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
+
+		setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});
 	}
 
 	void setup_stdcells()
 	{
-		setup_type("$_BUF_", {"\\A"}, {"\\Y"}, true);
-		setup_type("$_NOT_", {"\\A"}, {"\\Y"}, true);
-		setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, true);
-		setup_type("$_NAND_", {"\\A", "\\B"}, {"\\Y"}, true);
-		setup_type("$_OR_",  {"\\A", "\\B"}, {"\\Y"}, true);
-		setup_type("$_NOR_",  {"\\A", "\\B"}, {"\\Y"}, true);
-		setup_type("$_XOR_", {"\\A", "\\B"}, {"\\Y"}, true);
-		setup_type("$_XNOR_", {"\\A", "\\B"}, {"\\Y"}, true);
-		setup_type("$_MUX_", {"\\A", "\\B", "\\S"}, {"\\Y"}, true);
-		setup_type("$_AOI3_", {"\\A", "\\B", "\\C"}, {"\\Y"}, true);
-		setup_type("$_OAI3_", {"\\A", "\\B", "\\C"}, {"\\Y"}, true);
-		setup_type("$_AOI4_", {"\\A", "\\B", "\\C", "\\D"}, {"\\Y"}, true);
-		setup_type("$_OAI4_", {"\\A", "\\B", "\\C", "\\D"}, {"\\Y"}, true);
+		IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D", S = "\\S", Y = "\\Y";
+		setup_type("$_BUF_", {A}, {Y}, true);
+		setup_type("$_NOT_", {A}, {Y}, true);
+		setup_type("$_AND_", {A, B}, {Y}, true);
+		setup_type("$_NAND_", {A, B}, {Y}, true);
+		setup_type("$_OR_",  {A, B}, {Y}, true);
+		setup_type("$_NOR_",  {A, B}, {Y}, true);
+		setup_type("$_XOR_", {A, B}, {Y}, true);
+		setup_type("$_XNOR_", {A, B}, {Y}, true);
+		setup_type("$_MUX_", {A, B, S}, {Y}, true);
+		setup_type("$_AOI3_", {A, B, C}, {Y}, true);
+		setup_type("$_OAI3_", {A, B, C}, {Y}, true);
+		setup_type("$_AOI4_", {A, B, C, D}, {Y}, true);
+		setup_type("$_OAI4_", {A, B, C, D}, {Y}, true);
 	}
 
 	void setup_stdcells_mem()
 	{
+		IdString S = "\\S", R = "\\R", C = "\\C";
+		IdString D = "\\D", Q = "\\Q", E = "\\E";
+
 		std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
-			setup_type(stringf("$_SR_%c%c_", c1, c2), {"\\S", "\\R"}, {"\\Q"});
+			setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q});
 
 		for (auto c1 : list_np)
-			setup_type(stringf("$_DFF_%c_", c1), {"\\C", "\\D"}, {"\\Q"});
+			setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
-			setup_type(stringf("$_DFFE_%c%c_", c1, c2), {"\\C", "\\D", "\\E"}, {"\\Q"});
+			setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_01)
-			setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {"\\C", "\\R", "\\D"}, {"\\Q"});
+			setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_np)
-			setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {"\\C", "\\S", "\\R", "\\D"}, {"\\Q"});
+			setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q});
 
 		for (auto c1 : list_np)
-			setup_type(stringf("$_DLATCH_%c_", c1), {"\\E", "\\D"}, {"\\Q"});
+			setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q});
 
 		for (auto c1 : list_np)
 		for (auto c2 : list_np)
 		for (auto c3 : list_np)
-			setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {"\\E", "\\S", "\\R", "\\D"}, {"\\Q"});
+			setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q});
 	}
 
 	void clear()
@@ -368,6 +382,9 @@ struct CellTypes
 	}
 };
 
+// initialized by yosys_setup()
+extern CellTypes yosys_celltypes;
+
 YOSYS_NAMESPACE_END
 
 #endif
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6bc8dd0b..444bdb1d 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -18,6 +18,7 @@
  */
 
 #include "kernel/yosys.h"
+#include "kernel/celltypes.h"
 
 #ifdef YOSYS_ENABLE_READLINE
 #  include <readline/readline.h>
@@ -51,6 +52,7 @@ YOSYS_NAMESPACE_BEGIN
 int autoidx = 1;
 int yosys_xtrace = 0;
 RTLIL::Design *yosys_design = NULL;
+CellTypes yosys_celltypes;
 
 #ifdef YOSYS_ENABLE_TCL
 Tcl_Interp *yosys_tcl_interp = NULL;
@@ -378,8 +380,14 @@ int GetSize(RTLIL::Wire *wire)
 
 void yosys_setup()
 {
+	// if there are already IdString objects then we have a global initialization order bug
+	IdString empty_id;
+	log_assert(empty_id.index_ == 0);
+	IdString::get_reference(empty_id.index_);
+
 	Pass::init_register();
 	yosys_design = new RTLIL::Design;
+	yosys_celltypes.setup();
 	log_push();
 }
 
@@ -397,6 +405,7 @@ void yosys_shutdown()
 	log_files.clear();
 
 	Pass::done_register();
+	yosys_celltypes.clear();
 
 #ifdef YOSYS_ENABLE_TCL
 	if (yosys_tcl_interp != NULL) {