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authorClifford Wolf <clifford@clifford.at>2014-07-28 12:12:13 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-28 12:12:13 +0200
commit3c45277ee0f5822181c6058f679de632f834e7d2 (patch)
tree7bdf9f8d7a57a3744dc8d869343c710ca1055f1c /kernel
parent7bd2d1064f2eceddc3c93c121c4154a2f594a040 (diff)
Added wire->upto flag for signals such as "wire [0:7] x;"
Diffstat (limited to 'kernel')
-rw-r--r--kernel/rtlil.cc2
-rw-r--r--kernel/rtlil.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 78328618..b562e2af 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1019,6 +1019,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
wire->port_id = other->port_id;
wire->port_input = other->port_input;
wire->port_output = other->port_output;
+ wire->upto = other->upto;
wire->attributes = other->attributes;
return wire;
}
@@ -1443,6 +1444,7 @@ RTLIL::Wire::Wire()
port_id = 0;
port_input = false;
port_output = false;
+ upto = false;
}
RTLIL::Memory::Memory()
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index d78a6df2..097af9d2 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -602,7 +602,7 @@ public:
RTLIL::IdString name;
int width, start_offset, port_id;
- bool port_input, port_output;
+ bool port_input, port_output, upto;
RTLIL_ATTRIBUTE_MEMBERS
};