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authorClifford Wolf <clifford@clifford.at>2014-10-10 16:59:44 +0200
committerClifford Wolf <clifford@clifford.at>2014-10-10 17:07:24 +0200
commit4569a747f8af3880e23408eb93323afc8088b78b (patch)
tree81dcea51020173cd4951e8649f8bd8305e7c2591 /kernel
parentc7f5aab625bb90e766c1852592fdf42c951716c0 (diff)
Renamed SIZE() to GetSize() because of name collision on Win32
Diffstat (limited to 'kernel')
-rw-r--r--kernel/calc.cc2
-rw-r--r--kernel/celltypes.h12
-rw-r--r--kernel/consteval.h20
-rw-r--r--kernel/cost.h2
-rw-r--r--kernel/log.cc4
-rw-r--r--kernel/macc.h58
-rw-r--r--kernel/modtools.h6
-rw-r--r--kernel/rtlil.cc58
-rw-r--r--kernel/satgen.h64
-rw-r--r--kernel/sigtools.h8
-rw-r--r--kernel/utils.h6
-rw-r--r--kernel/yosys.cc10
-rw-r--r--kernel/yosys.h4
13 files changed, 127 insertions, 127 deletions
diff --git a/kernel/calc.cc b/kernel/calc.cc
index 41179d04..aa3e8b91 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -303,7 +303,7 @@ RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
- extend_u0(arg1_ext, std::max(result_len, SIZE(arg1)), signed1);
+ extend_u0(arg1_ext, std::max(result_len, GetSize(arg1)), signed1);
return const_shift_worker(arg1_ext, arg2, false, +1, result_len);
}
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 2774073d..3d9e4cf9 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -303,7 +303,7 @@ struct CellTypes
int width = cell->parameters.at("\\WIDTH").as_int();
std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;
- while (SIZE(t) < (1 << width))
+ while (GetSize(t) < (1 << width))
t.push_back(RTLIL::S0);
t.resize(1 << width);
@@ -311,16 +311,16 @@ struct CellTypes
RTLIL::State sel = arg1.bits.at(i);
std::vector<RTLIL::State> new_t;
if (sel == RTLIL::S0)
- new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + SIZE(t)/2);
+ new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
else if (sel == RTLIL::S1)
- new_t = std::vector<RTLIL::State>(t.begin() + SIZE(t)/2, t.end());
+ new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
else
- for (int j = 0; j < SIZE(t)/2; j++)
- new_t.push_back(t[j] == t[j + SIZE(t)/2] ? t[j] : RTLIL::Sx);
+ for (int j = 0; j < GetSize(t)/2; j++)
+ new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
t.swap(new_t);
}
- log_assert(SIZE(t) == 1);
+ log_assert(GetSize(t) == 1);
return t;
}
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 12895ec7..c2e9710f 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -74,7 +74,7 @@ struct ConstEval
assign_map.apply(sig);
#ifndef NDEBUG
RTLIL::SigSpec current_val = values_map(sig);
- for (int i = 0; i < SIZE(current_val); i++)
+ for (int i = 0; i < GetSize(current_val); i++)
log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
#endif
values_map.add(sig, RTLIL::SigSpec(value));
@@ -109,10 +109,10 @@ struct ConstEval
if (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())
{
- RTLIL::Const coval(RTLIL::Sx, SIZE(sig_co));
+ RTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));
bool carry = sig_ci.as_bool();
- for (int i = 0; i < SIZE(coval); i++) {
+ for (int i = 0; i < GetSize(coval); i++) {
carry = (sig_g[i] == RTLIL::S1) || (sig_p[i] == RTLIL::S1 && carry);
coval.bits[i] = carry ? RTLIL::S1 : RTLIL::S0;
}
@@ -120,7 +120,7 @@ struct ConstEval
set(sig_co, coval);
}
else
- set(sig_co, RTLIL::Const(RTLIL::Sx, SIZE(sig_co)));
+ set(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));
return true;
}
@@ -198,7 +198,7 @@ struct ConstEval
{
RTLIL::SigSpec sig_c = cell->getPort("\\C");
RTLIL::SigSpec sig_x = cell->getPort("\\X");
- int width = SIZE(sig_c);
+ int width = GetSize(sig_c);
if (!eval(sig_a, undef, cell))
return false;
@@ -216,7 +216,7 @@ struct ConstEval
RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);
RTLIL::Const val_x = const_or(t2, t3, false, false, width);
- for (int i = 0; i < SIZE(val_y); i++)
+ for (int i = 0; i < GetSize(val_y); i++)
if (val_y.bits[i] == RTLIL::Sx)
val_x.bits[i] = RTLIL::Sx;
@@ -247,13 +247,13 @@ struct ConstEval
RTLIL::SigSpec sig_co = cell->getPort("\\CO");
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
- sig_a.extend_u0(SIZE(sig_y), signed_a);
- sig_b.extend_u0(SIZE(sig_y), signed_b);
+ sig_a.extend_u0(GetSize(sig_y), signed_a);
+ sig_b.extend_u0(GetSize(sig_y), signed_b);
bool carry = sig_ci[0] == RTLIL::S1;
bool b_inv = sig_bi[0] == RTLIL::S1;
- for (int i = 0; i < SIZE(sig_y); i++)
+ for (int i = 0; i < GetSize(sig_y); i++)
{
RTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };
@@ -294,7 +294,7 @@ struct ConstEval
return false;
}
- RTLIL::Const result(0, SIZE(cell->getPort("\\Y")));
+ RTLIL::Const result(0, GetSize(cell->getPort("\\Y")));
if (!macc.eval(result))
log_abort();
diff --git a/kernel/cost.h b/kernel/cost.h
index 17aca837..5e99df99 100644
--- a/kernel/cost.h
+++ b/kernel/cost.h
@@ -70,7 +70,7 @@ int get_cell_cost(RTLIL::IdString type, const std::map<RTLIL::IdString, RTLIL::C
return module_cost;
}
- log("Warning: Can't determine cost of %s cell (%d parameters).\n", log_id(type), SIZE(parameters));
+ log("Warning: Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
return 1;
}
diff --git a/kernel/log.cc b/kernel/log.cc
index 1b0eb664..87a75410 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -62,9 +62,9 @@ void logv(const char *format, va_list ap)
size_t nnl_pos = str.find_last_not_of('\n');
if (nnl_pos == std::string::npos)
- log_newline_count += SIZE(str);
+ log_newline_count += GetSize(str);
else
- log_newline_count = SIZE(str) - nnl_pos - 1;
+ log_newline_count = GetSize(str) - nnl_pos - 1;
if (log_hasher)
log_hasher->update(str);
diff --git a/kernel/macc.h b/kernel/macc.h
index 7d70a268..ab17f8c4 100644
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -42,20 +42,20 @@ struct Macc
for (auto &port : ports)
{
- if (SIZE(port.in_a) == 0 && SIZE(port.in_b) == 0)
+ if (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)
continue;
- if (SIZE(port.in_a) < SIZE(port.in_b))
+ if (GetSize(port.in_a) < GetSize(port.in_b))
std::swap(port.in_a, port.in_b);
- if (SIZE(port.in_a) == 1 && SIZE(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {
+ if (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {
bit_ports.append(port.in_a);
continue;
}
if (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {
RTLIL::Const v = port.in_a.as_const();
- if (SIZE(port.in_b))
+ if (GetSize(port.in_b))
v = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);
if (port.do_subtract)
off = const_sub(off, v, port.is_signed, port.is_signed, width);
@@ -65,15 +65,15 @@ struct Macc
}
if (port.is_signed) {
- while (SIZE(port.in_a) > 1 && port.in_a[SIZE(port.in_a)-1] == port.in_a[SIZE(port.in_a)-2])
- port.in_a.remove(SIZE(port.in_a)-1);
- while (SIZE(port.in_b) > 1 && port.in_b[SIZE(port.in_b)-1] == port.in_b[SIZE(port.in_b)-2])
- port.in_b.remove(SIZE(port.in_b)-1);
+ while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])
+ port.in_a.remove(GetSize(port.in_a)-1);
+ while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])
+ port.in_b.remove(GetSize(port.in_b)-1);
} else {
- while (SIZE(port.in_a) > 1 && port.in_a[SIZE(port.in_a)-1] == RTLIL::S0)
- port.in_a.remove(SIZE(port.in_a)-1);
- while (SIZE(port.in_b) > 1 && port.in_b[SIZE(port.in_b)-1] == RTLIL::S0)
- port.in_b.remove(SIZE(port.in_b)-1);
+ while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == RTLIL::S0)
+ port.in_a.remove(GetSize(port.in_a)-1);
+ while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == RTLIL::S0)
+ port.in_b.remove(GetSize(port.in_b)-1);
}
new_ports.push_back(port);
@@ -108,7 +108,7 @@ struct Macc
int config_width = cell->getParam("\\CONFIG_WIDTH").as_int();
int config_cursor = 0;
- log_assert(SIZE(config_bits) >= config_width);
+ log_assert(GetSize(config_bits) >= config_width);
int num_bits = 0;
if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 1;
@@ -117,7 +117,7 @@ struct Macc
if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 8;
int port_a_cursor = 0;
- while (port_a_cursor < SIZE(port_a))
+ while (port_a_cursor < GetSize(port_a))
{
log_assert(config_cursor + 2 + 2*num_bits <= config_width);
@@ -146,7 +146,7 @@ struct Macc
}
log_assert(config_cursor == config_width);
- log_assert(port_a_cursor == SIZE(port_a));
+ log_assert(port_a_cursor == GetSize(port_a));
}
void to_cell(RTLIL::Cell *cell) const
@@ -156,8 +156,8 @@ struct Macc
int max_size = 0, num_bits = 0;
for (auto &port : ports) {
- max_size = std::max(max_size, SIZE(port.in_a));
- max_size = std::max(max_size, SIZE(port.in_b));
+ max_size = std::max(max_size, GetSize(port.in_a));
+ max_size = std::max(max_size, GetSize(port.in_b));
}
while (max_size)
@@ -171,17 +171,17 @@ struct Macc
for (auto &port : ports)
{
- if (SIZE(port.in_a) == 0)
+ if (GetSize(port.in_a) == 0)
continue;
config_bits.push_back(port.is_signed ? RTLIL::S1 : RTLIL::S0);
config_bits.push_back(port.do_subtract ? RTLIL::S1 : RTLIL::S0);
- int size_a = SIZE(port.in_a);
+ int size_a = GetSize(port.in_a);
for (int i = 0; i < num_bits; i++)
config_bits.push_back(size_a & (1 << i) ? RTLIL::S1 : RTLIL::S0);
- int size_b = SIZE(port.in_b);
+ int size_b = GetSize(port.in_b);
for (int i = 0; i < num_bits; i++)
config_bits.push_back(size_b & (1 << i) ? RTLIL::S1 : RTLIL::S0);
@@ -192,9 +192,9 @@ struct Macc
cell->setPort("\\A", port_a);
cell->setPort("\\B", bit_ports);
cell->setParam("\\CONFIG", config_bits);
- cell->setParam("\\CONFIG_WIDTH", SIZE(config_bits));
- cell->setParam("\\A_WIDTH", SIZE(port_a));
- cell->setParam("\\B_WIDTH", SIZE(bit_ports));
+ cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits));
+ cell->setParam("\\A_WIDTH", GetSize(port_a));
+ cell->setParam("\\B_WIDTH", GetSize(bit_ports));
}
bool eval(RTLIL::Const &result) const
@@ -208,21 +208,21 @@ struct Macc
return false;
RTLIL::Const summand;
- if (SIZE(port.in_b) == 0)
- summand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, SIZE(result));
+ if (GetSize(port.in_b) == 0)
+ summand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));
else
- summand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, SIZE(result));
+ summand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));
if (port.do_subtract)
- result = const_sub(result, summand, port.is_signed, port.is_signed, SIZE(result));
+ result = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));
else
- result = const_add(result, summand, port.is_signed, port.is_signed, SIZE(result));
+ result = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));
}
for (auto bit : bit_ports) {
if (bit.wire)
return false;
- result = const_add(result, bit.data, false, false, SIZE(result));
+ result = const_add(result, bit.data, false, false, GetSize(result));
}
return true;
diff --git a/kernel/modtools.h b/kernel/modtools.h
index 58cdd5b0..1b6968d7 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -59,7 +59,7 @@ struct ModIndex : public RTLIL::Monitor
void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
- for (int i = 0; i < SIZE(sig); i++) {
+ for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.insert(PortInfo(cell, port, i));
@@ -68,7 +68,7 @@ struct ModIndex : public RTLIL::Monitor
void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
- for (int i = 0; i < SIZE(sig); i++) {
+ for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.erase(PortInfo(cell, port, i));
@@ -88,7 +88,7 @@ struct ModIndex : public RTLIL::Monitor
database.clear();
for (auto wire : module->wires())
if (wire->port_input || wire->port_output)
- for (int i = 0; i < SIZE(wire); i++) {
+ for (int i = 0; i < GetSize(wire); i++) {
RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));
if (bit.wire && wire->port_input)
database[bit].is_input = true;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 89132ea2..28f0dfdc 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -941,10 +941,10 @@ void RTLIL::Module::check()
for (auto &it2 : it.second->attributes)
log_assert(!it2.first.empty());
if (it.second->port_id) {
- log_assert(SIZE(ports) >= it.second->port_id);
+ log_assert(GetSize(ports) >= it.second->port_id);
log_assert(ports.at(it.second->port_id-1) == it.first);
log_assert(it.second->port_input || it.second->port_output);
- if (SIZE(ports_declared) < it.second->port_id)
+ if (GetSize(ports_declared) < it.second->port_id)
ports_declared.resize(it.second->port_id);
log_assert(ports_declared[it.second->port_id-1] == false);
ports_declared[it.second->port_id-1] = true;
@@ -953,7 +953,7 @@ void RTLIL::Module::check()
}
for (auto port_declared : ports_declared)
log_assert(port_declared == true);
- log_assert(SIZE(ports) == SIZE(ports_declared));
+ log_assert(GetSize(ports) == GetSize(ports_declared));
for (auto &it : memories) {
log_assert(it.first == it.second->name);
@@ -1811,25 +1811,25 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
return;
if (type == "$mux" || type == "$pmux") {
- parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
if (type == "$pmux")
- parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
+ parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
check();
return;
}
if (type == "$lut") {
- parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
return;
}
if (type == "$fa") {
- parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
return;
}
if (type == "$lcu") {
- parameters["\\WIDTH"] = SIZE(connections_["\\CO"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
return;
}
@@ -1842,7 +1842,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
else if (parameters.count("\\A_SIGNED") == 0)
parameters["\\A_SIGNED"] = false;
}
- parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
+ parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
}
if (connections_.count("\\B")) {
@@ -1852,11 +1852,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
else if (parameters.count("\\B_SIGNED") == 0)
parameters["\\B_SIGNED"] = false;
}
- parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
+ parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
}
if (connections_.count("\\Y"))
- parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
+ parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
check();
}
@@ -1872,7 +1872,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
{
wire = NULL;
data = value.bits;
- width = SIZE(data);
+ width = GetSize(data);
offset = 0;
}
@@ -1896,7 +1896,7 @@ RTLIL::SigChunk::SigChunk(const std::string &str)
{
wire = NULL;
data = RTLIL::Const(str).bits;
- width = SIZE(data);
+ width = GetSize(data);
offset = 0;
}
@@ -1904,7 +1904,7 @@ RTLIL::SigChunk::SigChunk(int val, int width)
{
wire = NULL;
data = RTLIL::Const(val, width).bits;
- this->width = SIZE(data);
+ this->width = GetSize(data);
offset = 0;
}
@@ -1912,7 +1912,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
{
wire = NULL;
data = RTLIL::Const(bit, width).bits;
- this->width = SIZE(data);
+ this->width = GetSize(data);
offset = 0;
}
@@ -2258,7 +2258,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
- for (int i = 0; i < SIZE(pattern.bits_); i++)
+ for (int i = 0; i < GetSize(pattern.bits_); i++)
if (pattern.bits_[i].wire != NULL)
rules[pattern.bits_[i]] = with.bits_[i];
@@ -2280,7 +2280,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
unpack();
other->unpack();
- for (int i = 0; i < SIZE(bits_); i++) {
+ for (int i = 0; i < GetSize(bits_); i++) {
auto it = rules.find(bits_[i]);
if (it != rules.end())
other->bits_[i] = it->second;
@@ -2333,12 +2333,12 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
std::vector<RTLIL::SigBit> new_bits, new_other_bits;
- new_bits.resize(SIZE(bits_));
+ new_bits.resize(GetSize(bits_));
if (other != NULL)
- new_other_bits.resize(SIZE(bits_));
+ new_other_bits.resize(GetSize(bits_));
int k = 0;
- for (int i = 0; i < SIZE(bits_); i++) {
+ for (int i = 0; i < GetSize(bits_); i++) {
if (bits_[i].wire != NULL && pattern.count(bits_[i]))
continue;
if (other != NULL)
@@ -2351,11 +2351,11 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
new_other_bits.resize(k);
bits_.swap(new_bits);
- width_ = SIZE(bits_);
+ width_ = GetSize(bits_);
if (other != NULL) {
other->bits_.swap(new_other_bits);
- other->width_ = SIZE(other->bits_);
+ other->width_ = GetSize(other->bits_);
}
check();
@@ -2418,7 +2418,7 @@ void RTLIL::SigSpec::remove_const()
cover("kernel.rtlil.sigspec.remove_const.packed");
std::vector<RTLIL::SigChunk> new_chunks;
- new_chunks.reserve(SIZE(chunks_));
+ new_chunks.reserve(GetSize(chunks_));
width_ = 0;
for (auto &chunk : chunks_)
@@ -2624,7 +2624,7 @@ void RTLIL::SigSpec::check() const
{
cover("kernel.rtlil.sigspec.check.unpacked");
- log_assert(width_ == SIZE(bits_));
+ log_assert(width_ == GetSize(bits_));
log_assert(chunks_.empty());
}
}
@@ -2699,7 +2699,7 @@ bool RTLIL::SigSpec::is_wire() const
cover("kernel.rtlil.sigspec.is_wire");
pack();
- return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
+ return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
}
bool RTLIL::SigSpec::is_chunk() const
@@ -2707,7 +2707,7 @@ bool RTLIL::SigSpec::is_chunk() const
cover("kernel.rtlil.sigspec.is_chunk");
pack();
- return SIZE(chunks_) == 1;
+ return GetSize(chunks_) == 1;
}
bool RTLIL::SigSpec::is_fully_const() const
@@ -2770,7 +2770,7 @@ bool RTLIL::SigSpec::as_bool() const
cover("kernel.rtlil.sigspec.as_bool");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
return RTLIL::Const(chunks_[0].data).as_bool();
return false;
@@ -2781,7 +2781,7 @@ int RTLIL::SigSpec::as_int(bool is_signed) const
cover("kernel.rtlil.sigspec.as_int");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
return RTLIL::Const(chunks_[0].data).as_int(is_signed);
return 0;
@@ -2809,7 +2809,7 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
cover("kernel.rtlil.sigspec.as_const");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
return chunks_[0].data;
return RTLIL::Const();
diff --git a/kernel/satgen.h b/kernel/satgen.h
index d4933050..2759b392 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -59,7 +59,7 @@ struct SatGen
sigmap->apply(sig);
std::vector<int> vec;
- vec.reserve(SIZE(sig));
+ vec.reserve(GetSize(sig));
for (auto &bit : sig)
if (bit.wire == NULL) {
@@ -791,24 +791,24 @@ struct SatGen
Macc macc;
macc.from_cell(cell);
- std::vector<int> tmp(SIZE(y), ez->FALSE);
+ std::vector<int> tmp(GetSize(y), ez->FALSE);
for (auto &port : macc.ports)
{
std::vector<int> in_a = importDefSigSpec(port.in_a, timestep);
std::vector<int> in_b = importDefSigSpec(port.in_b, timestep);
- while (SIZE(in_a) < SIZE(y))
+ while (GetSize(in_a) < GetSize(y))
in_a.push_back(port.is_signed && !in_a.empty() ? in_a.back() : ez->FALSE);
- in_a.resize(SIZE(y));
+ in_a.resize(GetSize(y));
- if (SIZE(in_b))
+ if (GetSize(in_b))
{
- while (SIZE(in_b) < SIZE(y))
+ while (GetSize(in_b) < GetSize(y))
in_b.push_back(port.is_signed && !in_b.empty() ? in_b.back() : ez->FALSE);
- in_b.resize(SIZE(y));
+ in_b.resize(GetSize(y));
- for (int i = 0; i < SIZE(in_b); i++) {
+ for (int i = 0; i < GetSize(in_b); i++) {
std::vector<int> shifted_a(in_a.size(), ez->FALSE);
for (int j = i; j < int(in_a.size()); j++)
shifted_a.at(j) = in_a.at(j-i);
@@ -827,8 +827,8 @@ struct SatGen
}
}
- for (int i = 0; i < SIZE(b); i++) {
- std::vector<int> val(SIZE(y), ez->FALSE);
+ for (int i = 0; i < GetSize(b); i++) {
+ std::vector<int> val(GetSize(y), ez->FALSE);
val.at(0) = b.at(i);
tmp = ez->vec_add(tmp, val);
}
@@ -842,7 +842,7 @@ struct SatGen
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
- ez->assume(ez->vec_eq(undef_y, std::vector<int>(SIZE(y), ez->OR(undef_any_a, undef_any_b))));
+ ez->assume(ez->vec_eq(undef_y, std::vector<int>(GetSize(y), ez->OR(undef_any_a, undef_any_b))));
undefGating(y, tmp, undef_y);
}
@@ -940,43 +940,43 @@ struct SatGen
std::vector<int> lut;
for (auto bit : cell->getParam("\\LUT").bits)
lut.push_back(bit == RTLIL::S1 ? ez->TRUE : ez->FALSE);
- while (SIZE(lut) < (1 << SIZE(a)))
+ while (GetSize(lut) < (1 << GetSize(a)))
lut.push_back(ez->FALSE);
- lut.resize(1 << SIZE(a));
+ lut.resize(1 << GetSize(a));
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
- std::vector<int> t(lut), u(SIZE(t), ez->FALSE);
+ std::vector<int> t(lut), u(GetSize(t), ez->FALSE);
- for (int i = SIZE(a)-1; i >= 0; i--)
+ for (int i = GetSize(a)-1; i >= 0; i--)
{
- std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
- std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
+ std::vector<int> t0(t.begin(), t.begin() + GetSize(t)/2);
+ std::vector<int> t1(t.begin() + GetSize(t)/2, t.end());
- std::vector<int> u0(u.begin(), u.begin() + SIZE(u)/2);
- std::vector<int> u1(u.begin() + SIZE(u)/2, u.end());
+ std::vector<int> u0(u.begin(), u.begin() + GetSize(u)/2);
+ std::vector<int> u1(u.begin() + GetSize(u)/2, u.end());
t = ez->vec_ite(a[i], t1, t0);
u = ez->vec_ite(undef_a[i], ez->vec_or(ez->vec_xor(t0, t1), ez->vec_or(u0, u1)), ez->vec_ite(a[i], u1, u0));
}
- log_assert(SIZE(t) == 1);
- log_assert(SIZE(u) == 1);
+ log_assert(GetSize(t) == 1);
+ log_assert(GetSize(u) == 1);
undefGating(y, t, u);
ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort("\\Y"), timestep), u));
}
else
{
std::vector<int> t = lut;
- for (int i = SIZE(a)-1; i >= 0; i--)
+ for (int i = GetSize(a)-1; i >= 0; i--)
{
- std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
- std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
+ std::vector<int> t0(t.begin(), t.begin() + GetSize(t)/2);
+ std::vector<int> t1(t.begin() + GetSize(t)/2, t.end());
t = ez->vec_ite(a[i], t1, t0);
}
- log_assert(SIZE(t) == 1);
+ log_assert(GetSize(t) == 1);
ez->assume(ez->vec_eq(y, t));
}
return true;
@@ -1027,7 +1027,7 @@ struct SatGen
std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
- for (int i = 0; i < SIZE(co); i++)
+ for (int i = 0; i < GetSize(co); i++)
ez->SET(yy[i], ez->OR(g[i], ez->AND(p[i], i ? yy[i-1] : ci[0])));
if (model_undef)
@@ -1068,12 +1068,12 @@ struct SatGen
std::vector<int> def_x = model_undef ? ez->vec_var(x.size()) : x;
std::vector<int> def_co = model_undef ? ez->vec_var(co.size()) : co;
- log_assert(SIZE(y) == SIZE(x));
- log_assert(SIZE(y) == SIZE(co));
- log_assert(SIZE(ci) == 1);
- log_assert(SIZE(bi) == 1);
+ log_assert(GetSize(y) == GetSize(x));
+ log_assert(GetSize(y) == GetSize(co));
+ log_assert(GetSize(ci) == 1);
+ log_assert(GetSize(bi) == 1);
- for (int i = 0; i < SIZE(y); i++)
+ for (int i = 0; i < GetSize(y); i++)
{
int s1 = a.at(i), s2 = ez->XOR(b.at(i), bi.at(0)), s3 = i ? co.at(i-1) : ci.at(0);
ez->SET(def_x.at(i), ez->XOR(s1, s2));
@@ -1103,7 +1103,7 @@ struct SatGen
all_inputs_undef.insert(all_inputs_undef.end(), undef_bi.begin(), undef_bi.end());
int undef_any = ez->expression(ezSAT::OpOr, all_inputs_undef);
- for (int i = 0; i < SIZE(undef_y); i++) {
+ for (int i = 0; i < GetSize(undef_y); i++) {
ez->SET(undef_y.at(i), undef_any);
ez->SET(undef_x.at(i), ez->OR(undef_a.at(i), undef_b.at(i), undef_bi.at(0)));
ez->SET(undef_co.at(i), undef_any);
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 32ef444a..c3c6a8db 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -66,8 +66,8 @@ struct SigPool
void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
- log_assert(SIZE(from) == SIZE(to));
- for (int i = 0; i < SIZE(from); i++) {
+ log_assert(GetSize(from) == GetSize(to));
+ for (int i = 0; i < GetSize(from); i++) {
bitDef_t bit_from(from[i]), bit_to(to[i]);
if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)
bits.insert(bit_to);
@@ -346,9 +346,9 @@ struct SigMap
void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
- log_assert(SIZE(from) == SIZE(to));
+ log_assert(GetSize(from) == GetSize(to));
- for (int i = 0; i < SIZE(from); i++)
+ for (int i = 0; i < GetSize(from); i++)
{
RTLIL::SigBit &bf = from[i];
RTLIL::SigBit &bt = to[i];
diff --git a/kernel/utils.h b/kernel/utils.h
index 264558b8..1779a9af 100644
--- a/kernel/utils.h
+++ b/kernel/utils.h
@@ -83,7 +83,7 @@ public:
void reset(const Key &k)
{
- for (int i = SIZE(backup_state)-1; i >= 0; i--)
+ for (int i = GetSize(backup_state)-1; i >= 0; i--)
if (backup_state[i].count(k) != 0) {
if (backup_state[i].at(k) == nullptr)
current_state.erase(k);
@@ -160,7 +160,7 @@ struct TopoSort
found_loops = true;
if (analyze_loops) {
std::set<T> loop;
- for (int i = SIZE(active_stack)-1; i >= 0; i--) {
+ for (int i = GetSize(active_stack)-1; i >= 0; i--) {
loop.insert(active_stack[i]);
if (active_stack[i] == n)
break;
@@ -204,7 +204,7 @@ struct TopoSort
for (auto &it : database)
sort_worker(it.first, marked_cells, active_cells, active_stack);
- log_assert(SIZE(sorted) == SIZE(database));
+ log_assert(GetSize(sorted) == GetSize(database));
return !found_loops;
}
};
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 0ecb4cda..971da78a 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -66,7 +66,7 @@ std::string vstringf(const char *fmt, va_list ap)
return string;
}
-int SIZE(RTLIL::Wire *wire)
+int GetSize(RTLIL::Wire *wire)
{
return wire->width;
}
@@ -275,15 +275,15 @@ static void handle_label(std::string &command, bool &from_to_active, const std::
int pos = 0;
std::string label;
- while (pos < SIZE(command) && (command[pos] == ' ' || command[pos] == '\t'))
+ while (pos < GetSize(command) && (command[pos] == ' ' || command[pos] == '\t'))
pos++;
- while (pos < SIZE(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n')
+ while (pos < GetSize(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n')
label += command[pos++];
- if (label.back() == ':' && SIZE(label) > 1)
+ if (label.back() == ':' && GetSize(label) > 1)
{
- label = label.substr(0, SIZE(label)-1);
+ label = label.substr(0, GetSize(label)-1);
command = command.substr(pos);
if (label == run_from)
diff --git a/kernel/yosys.h b/kernel/yosys.h
index e796919f..c5da9f04 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -84,8 +84,8 @@ namespace RTLIL {
std::string stringf(const char *fmt, ...);
std::string vstringf(const char *fmt, va_list ap);
-template<typename T> int SIZE(const T &obj) { return obj.size(); }
-int SIZE(RTLIL::Wire *wire);
+template<typename T> int GetSize(const T &obj) { return obj.size(); }
+int GetSize(RTLIL::Wire *wire);
YOSYS_NAMESPACE_END