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authorClifford Wolf <clifford@clifford.at>2014-09-03 13:39:46 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-03 13:39:46 +0200
commit50ac2848239cf5969b80c427a95b6098fd1e2f1c (patch)
tree1bf470c093e08e54c5223a60ee0b4daa2fc14ece /kernel
parent635b922afeabea8c69ac4e749881b10aeda7448b (diff)
Fixes in $alu SAT- and eval-models
Diffstat (limited to 'kernel')
-rw-r--r--kernel/consteval.h4
-rw-r--r--kernel/satgen.h7
2 files changed, 5 insertions, 6 deletions
diff --git a/kernel/consteval.h b/kernel/consteval.h
index fb54b72f..c73a0b35 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -178,8 +178,8 @@ struct ConstEval
RTLIL::SigSpec sig_co = cell->getPort("\\CO");
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
- sig_a.extend(SIZE(sig_y), signed_a);
- sig_b.extend(SIZE(sig_y), signed_b);
+ sig_a.extend_u0(SIZE(sig_y), signed_a);
+ sig_b.extend_u0(SIZE(sig_y), signed_b);
bool carry = sig_ci[0] == RTLIL::S1;
bool b_inv = sig_bi[0] == RTLIL::S1;
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 3685cd6e..c7f1680d 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -934,9 +934,9 @@ struct SatGen
std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep);
- extendSignalWidth(undef_a, undef_b, undef_y, cell, true);
- extendSignalWidth(undef_a, undef_b, undef_x, cell, true);
- extendSignalWidth(undef_a, undef_b, undef_co, cell, true);
+ extendSignalWidth(undef_a, undef_b, undef_y, cell);
+ extendSignalWidth(undef_a, undef_b, undef_x, cell);
+ extendSignalWidth(undef_a, undef_b, undef_co, cell);
std::vector<int> all_inputs_undef;
all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end());
@@ -955,7 +955,6 @@ struct SatGen
undefGating(x, def_x, undef_x);
undefGating(co, def_co, undef_co);
}
- log_ping();
return true;
}