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authorClifford Wolf <clifford@clifford.at>2013-11-23 15:58:06 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-23 15:58:06 +0100
commit532091afcbb8ba547392f51ba3a020d993e099da (patch)
treef8655ebf265301120dd3e8bf43c749f2a80442dd /kernel
parent9ab850e45eb907a6778c62eace974221d18b49c2 (diff)
Added more generic _TECHMAP_ wire mechanism to techmap pass
Diffstat (limited to 'kernel')
-rw-r--r--kernel/rtlil.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 52bf6e80..c7f9cf12 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -204,6 +204,12 @@ struct RTLIL::Selection {
bool selected_whole_module(RTLIL::IdString mod_name) const;
bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
void optimize(RTLIL::Design *design);
+ template<typename T1> void select(T1 *module) {
+ if (!full_selection && selected_modules.count(module->name) == 0) {
+ selected_modules.insert(module->name);
+ selected_members.erase(module->name);
+ }
+ }
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (!full_selection && selected_modules.count(module->name) == 0)
selected_members[module->name].insert(member->name);