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authorClifford Wolf <clifford@clifford.at>2014-09-04 02:07:52 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-04 02:07:52 +0200
commit8927aa6148f5575b2da9bfb76afb4af076fe18f3 (patch)
tree4da0980333589d4785880e48383c6f44e4a94887 /kernel
parentb9cb483f3e2a498ee75a422e09164a920918362b (diff)
Removed $bu0 cell type
Diffstat (limited to 'kernel')
-rw-r--r--kernel/calc.cc21
-rw-r--r--kernel/celltypes.h5
-rw-r--r--kernel/rtlil.cc3
-rw-r--r--kernel/rtlil.h2
-rw-r--r--kernel/satgen.h6
5 files changed, 6 insertions, 31 deletions
diff --git a/kernel/calc.cc b/kernel/calc.cc
index da03f616..41179d04 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -26,19 +26,6 @@
YOSYS_NAMESPACE_BEGIN
-static void extend(RTLIL::Const &arg, int width, bool is_signed)
-{
- RTLIL::State padding = RTLIL::State::S0;
-
- if (arg.bits.size() > 0 && (is_signed || arg.bits.back() > RTLIL::State::S1))
- padding = arg.bits.back();
-
- while (int(arg.bits.size()) < width)
- arg.bits.push_back(padding);
-
- arg.bits.resize(width);
-}
-
static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
{
RTLIL::State padding = RTLIL::State::S0;
@@ -580,14 +567,6 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo
return arg1_ext;
}
-RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
-{
- RTLIL::Const arg1_ext = arg1;
- extend_u0(arg1_ext, result_len, signed1);
-
- return arg1_ext;
-}
-
RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 4a8be04d..a8d88603 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -86,7 +86,7 @@ struct CellTypes
void setup_internals()
{
std::vector<RTLIL::IdString> unary_ops = {
- "$not", "$pos", "$bu0", "$neg",
+ "$not", "$pos", "$neg",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$logic_not", "$slice", "$lut"
};
@@ -219,7 +219,7 @@ struct CellTypes
type = "$shl";
if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && type != "$shift" && type != "$shiftx" &&
- type != "$pos" && type != "$neg" && type != "$not" && type != "$bu0") {
+ type != "$pos" && type != "$neg" && type != "$not") {
if (!signed1 || !signed2)
signed1 = false, signed2 = false;
}
@@ -259,7 +259,6 @@ struct CellTypes
HANDLE_CELL_TYPE(mod)
HANDLE_CELL_TYPE(pow)
HANDLE_CELL_TYPE(pos)
- HANDLE_CELL_TYPE(bu0)
HANDLE_CELL_TYPE(neg)
#undef HANDLE_CELL_TYPE
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 35cd54b4..08c79bea 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -563,7 +563,7 @@ namespace {
cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
return;
- if (cell->type.in("$not", "$pos", "$bu0", "$neg")) {
+ if (cell->type.in("$not", "$pos", "$neg")) {
param_bool("\\A_SIGNED");
port("\\A", param("\\A_WIDTH"));
port("\\Y", param("\\Y_WIDTH"));
@@ -1326,7 +1326,6 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
}
DEF_METHOD(Not, sig_a.size(), "$not")
DEF_METHOD(Pos, sig_a.size(), "$pos")
-DEF_METHOD(Bu0, sig_a.size(), "$bu0")
DEF_METHOD(Neg, sig_a.size(), "$neg")
DEF_METHOD(ReduceAnd, 1, "$reduce_and")
DEF_METHOD(ReduceOr, 1, "$reduce_or")
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index b8733c4e..c4883769 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -314,7 +314,6 @@ namespace RTLIL
RTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_pos (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
- RTLIL::Const const_bu0 (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_neg (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
@@ -651,7 +650,6 @@ public:
RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
- RTLIL::Cell* addBu0 (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index eed3adaa..ae155a2e 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -451,7 +451,7 @@ struct SatGen
return true;
}
- if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg")
+ if (cell->type == "$pos" || cell->type == "$neg")
{
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
@@ -459,7 +459,7 @@ struct SatGen
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
- if (cell->type == "$pos" || cell->type == "$bu0") {
+ if (cell->type == "$pos") {
ez->assume(ez->vec_eq(a, yy));
} else {
std::vector<int> zero(a.size(), ez->FALSE);
@@ -472,7 +472,7 @@ struct SatGen
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell);
- if (cell->type == "$pos" || cell->type == "$bu0") {
+ if (cell->type == "$pos") {
ez->assume(ez->vec_eq(undef_a, undef_y));
} else {
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);