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authorClifford Wolf <clifford@clifford.at>2015-10-27 15:09:44 +0100
committerClifford Wolf <clifford@clifford.at>2015-10-27 15:09:44 +0100
commitf3db70d2f3d9e9c313df8d1e1880c170d3343ca8 (patch)
tree0c77f402b12364120f024a0d8632f217b6bddc99 /kernel
parent09b4050f2e6e02fd6252f8650bc206b401b7a683 (diff)
Removed old SigMap implementation
Diffstat (limited to 'kernel')
-rw-r--r--kernel/sigtools.h224
1 files changed, 0 insertions, 224 deletions
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index b382cdeb..3e19ac8c 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -220,7 +220,6 @@ struct SigSet
}
};
-#if 1
struct SigMap
{
mfp<SigBit> database;
@@ -231,17 +230,6 @@ struct SigMap
set(module);
}
- // SigMap(const SigMap &other)
- // {
- // copy(other);
- // }
-
- // const SigMap &operator=(const SigMap &other)
- // {
- // copy(other);
- // return *this;
- // }
-
void swap(SigMap &other)
{
database.swap(other.database);
@@ -309,218 +297,6 @@ struct SigMap
return sig;
}
};
-#else
-struct SigMap
-{
- struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
- bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
- bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
- unsigned int hash() const { return first->name.hash() + second; }
- };
-
- struct shared_bit_data_t {
- RTLIL::SigBit map_to;
- std::set<bitDef_t> bits;
- };
-
- dict<bitDef_t, shared_bit_data_t*> bits;
-
- SigMap(RTLIL::Module *module = NULL)
- {
- if (module != NULL)
- set(module);
- }
-
- SigMap(const SigMap &other)
- {
- copy(other);
- }
-
- const SigMap &operator=(const SigMap &other)
- {
- copy(other);
- return *this;
- }
-
- void copy(const SigMap &other)
- {
- clear();
- for (auto &bit : other.bits) {
- bits[bit.first] = new shared_bit_data_t;
- bits[bit.first]->map_to = bit.second->map_to;
- bits[bit.first]->bits = bit.second->bits;
- }
- }
-
- void swap(SigMap &other)
- {
- bits.swap(other.bits);
- }
-
- ~SigMap()
- {
- clear();
- }
-
- void clear()
- {
- std::set<shared_bit_data_t*> all_bd_ptr;
- for (auto &it : bits)
- all_bd_ptr.insert(it.second);
- for (auto bd_ptr : all_bd_ptr)
- delete bd_ptr;
- bits.clear();
- }
-
- void set(RTLIL::Module *module)
- {
- clear();
- for (auto &it : module->connections())
- add(it.first, it.second);
- }
-
- // internal helper function
- void register_bit(const RTLIL::SigBit &bit)
- {
- if (bit.wire && bits.count(bit) == 0) {
- shared_bit_data_t *bd = new shared_bit_data_t;
- bd->map_to = bit;
- bd->bits.insert(bit);
- bits[bit] = bd;
- }
- }
-
- // internal helper function
- void unregister_bit(const RTLIL::SigBit &bit)
- {
- if (bit.wire && bits.count(bit) > 0) {
- shared_bit_data_t *bd = bits[bit];
- bd->bits.erase(bit);
- if (bd->bits.size() == 0)
- delete bd;
- bits.erase(bit);
- }
- }
-
- // internal helper function
- void merge_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
- {
- log_assert(bit1.wire != NULL && bit2.wire != NULL);
-
- shared_bit_data_t *bd1 = bits[bit1];
- shared_bit_data_t *bd2 = bits[bit2];
- log_assert(bd1 != NULL && bd2 != NULL);
-
- if (bd1 == bd2)
- return;
-
- if (bd1->bits.size() < bd2->bits.size())
- {
- for (auto &bit : bd1->bits)
- bits[bit] = bd2;
- bd2->bits.insert(bd1->bits.begin(), bd1->bits.end());
- delete bd1;
- }
- else
- {
- bd1->map_to = bd2->map_to;
- for (auto &bit : bd2->bits)
- bits[bit] = bd1;
- bd1->bits.insert(bd2->bits.begin(), bd2->bits.end());
- delete bd2;
- }
- }
-
- // internal helper function
- void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
- {
- log_assert(bit1.wire != NULL);
- log_assert(bits.count(bit1) > 0);
- bits[bit1]->map_to = bit2;
- }
-
- // internal helper function
- void map_bit(RTLIL::SigBit &bit) const
- {
- if (bit.wire && bits.count(bit) > 0)
- bit = bits.at(bit)->map_to;
- }
-
- void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
- {
- log_assert(GetSize(from) == GetSize(to));
-
- for (int i = 0; i < GetSize(from); i++)
- {
- RTLIL::SigBit &bf = from[i];
- RTLIL::SigBit &bt = to[i];
-
- if (bf.wire == NULL)
- continue;
-
- register_bit(bf);
- register_bit(bt);
-
- if (bt.wire != NULL)
- merge_bit(bf, bt);
- else
- set_bit(bf, bt);
- }
- }
-
- void add(RTLIL::SigSpec sig)
- {
- for (auto &bit : sig) {
- register_bit(bit);
- set_bit(bit, bit);
- }
- }
-
- void del(RTLIL::SigSpec sig)
- {
- for (auto &bit : sig)
- unregister_bit(bit);
- }
-
- void apply(RTLIL::SigBit &bit) const
- {
- map_bit(bit);
- }
-
- void apply(RTLIL::SigSpec &sig) const
- {
- for (auto &bit : sig)
- map_bit(bit);
- }
-
- RTLIL::SigBit operator()(RTLIL::SigBit bit) const
- {
- apply(bit);
- return bit;
- }
-
- RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const
- {
- apply(sig);
- return sig;
- }
-
- RTLIL::SigSpec operator()(RTLIL::Wire *wire) const
- {
- RTLIL::SigSpec sig(wire);
- apply(sig);
- return sig;
- }
-
- RTLIL::SigSpec allbits() const
- {
- RTLIL::SigSpec sig;
- for (auto &it : bits)
- sig.append(SigBit(it.first.first, it.first.second));
- return sig;
- }
-};
-#endif
YOSYS_NAMESPACE_END