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| author | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-01-20 09:58:04 +0100 |
|---|---|---|
| committer | Ahmed Irfan <irfan@ubuntu.(none)> | 2014-01-20 09:58:04 +0100 |
| commit | b7adf4c7a0d0f561d08d7e4dcf66b4e651596318 (patch) | |
| tree | d5b7e8e79e7ab98eaca898f65c438f8aa1be5407 /manual/CHAPTER_CellLib.tex | |
| parent | 234d0d0e1c316d7253c56c522dcc982a5e6049a1 (diff) | |
| parent | 32a91458a7dde9994ca28ec635c1bec8fe20111b (diff) | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index b84e1b30..b848a2b6 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -418,3 +418,7 @@ from the gate level logic network can be mapped to physical flip-flop cells from pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC} using the {\tt abc} pass. +\begin{fixme} +Add information about {\tt \$assert} cells. +\end{fixme} + |