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| author | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:41:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:41:05 +0200 |
| commit | 647c23b7b7e3a72fc64d9b1ad07dacd590865898 (patch) | |
| tree | 4582f5a2d0ddc29f3940f0ae48fb108602fc388c /manual/CHAPTER_Overview.tex | |
| parent | 2c9bd23801fc00463cd218319c7f2f3a89852260 (diff) | |
Updated manual
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index f79f5f10..7d61a1d1 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -72,8 +72,9 @@ in different stages of the synthesis. \node[process] (astfe) [below of=ast, node distance=5em] {AST Frontend}; \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; - \node[process] (vlbe) [below of=rtlil, node distance=5em, xshift=-7.5em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=5em, xshift=+7.5em] {ILANG Backend}; + \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process, dashed, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); \draw[-latex] (vhdl) -- (ast); @@ -83,6 +84,7 @@ in different stages of the synthesis. \draw[latex-latex] (rtlil) -- (pass); \draw[-latex] (rtlil) -- (vlbe); \draw[-latex] (rtlil) -- (ilangbe); + \draw[-latex] (rtlil) -- (otherbe); \end{tikzpicture} \caption{Yosys simplified data flow (ellipses: data structures, rectangles: program modules)} \label{fig:Overview_flow} |