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authorRuben Undheim <ruben.undheim@gmail.com>2018-07-12 13:41:39 +0200
committerRuben Undheim <ruben.undheim@gmail.com>2019-10-18 23:27:34 +0200
commit12603432fed7e0332f09f34fad0bcc9aa88bd456 (patch)
tree6bfc694ec2b40f91e6c66b2d2a0ba67f5f044461 /manual/CHAPTER_Overview.tex
parent1a4451589002afcec33f9b098a3584fe4beae2f1 (diff)
Some spelling errors fixed
Gbp-Pq: Name 0009-Some-spelling-errors-fixed.patch
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
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diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 3009bf2c..4136efed 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -240,7 +240,7 @@ An RTLIL::Wire object has the following properties:
As with modules, the attributes can be Verilog attributes imported by the
Verilog frontend or attributes assigned by passes.
-In Yosys, busses (signal vectors) are represented using a single wire object
+In Yosys, buses (signal vectors) are represented using a single wire object
with a width > 1. So Yosys does not convert signal vectors to individual signals.
This makes some aspects of RTLIL more complex but enables Yosys to be used for
coarse grain synthesis where the cells of the target architecture operate on