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authorClifford Wolf <clifford@clifford.at>2013-07-25 14:00:16 +0200
committerClifford Wolf <clifford@clifford.at>2013-07-25 14:00:16 +0200
commit36c39cbd04c760a833cb746ac5c71d667d9c87a7 (patch)
treeec428ef65c66337f361ab8c3dd5bd50581d922bc /manual/CHAPTER_Overview.tex
parent88d0829d65c298d1918e4e4c3a01a00cc58780ba (diff)
Added RTLIL and Liberty syntax highlighting to manual
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
-rw-r--r--manual/CHAPTER_Overview.tex6
1 files changed, 3 insertions, 3 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 40deabfa..f79f5f10 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -300,7 +300,7 @@ In this example there is no data path and therefore the RTLIL::Module generated
the frontend only contains a few RTLIL::Wire objects and an RTLIL::Process.
The RTLIL::Process in ILANG syntax:
-\begin{lstlisting}[numbers=left,frame=single]
+\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
process $proc$ff_with_en_and_async_reset.v:4$1
assign $0\q[0:0] \q
switch \reset
@@ -364,7 +364,7 @@ One of the first actions performed on a design in RTLIL representation in most
synthesis scripts is identifying asynchronous resets. This is usually done using the {\tt proc\_arst}
pass. This pass transforms the above example to the following RTLIL::Process:
-\begin{lstlisting}[numbers=left,frame=single]
+\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
process $proc$ff_with_en_and_async_reset.v:4$1
assign $0\q[0:0] \q
switch \enable
@@ -383,7 +383,7 @@ This pass has transformed the outer RTLIL::SwitchRule into a modified RTLIL::Syn
for the {\tt \textbackslash{}reset} signal. Further processing converts the RTLIL::Process
e.g.~into a d-type flip-flop with asynchronous reset and a multiplexer for the enable signal:
-\begin{lstlisting}[numbers=left,frame=single]
+\begin{lstlisting}[numbers=left,frame=single,language=rtlil]
cell $adff $procdff$6
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'0