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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-03-28 23:35:03 +0100 |
| commit | ff5734b20220e6fb4a3913cf5279ed94bb5156ea (patch) | |
| tree | 4c438282926d7bac304ad3ad6ad89523c4c1d784 /manual/CHAPTER_Overview.tex | |
| parent | db3c67fd6e140893450a44870ee9a75dd1f48b27 (diff) | |
Imported GIT HEAD: 0.8+20190328git32bd0f2
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 964875d5..2feb0f1c 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -428,8 +428,8 @@ memory object has the following properties: All read accesses to the memory are transformed to {\tt \$memrd} cells and all write accesses to {\tt \$memwr} cells by the language frontend. These cells consist of independent read- and write-ports -to the memory. The \B{MEMID} parameter on these cells is used to link them together and to the -RTLIL::Memory object they belong to. +to the memory. Memory initialization is transformed to {\tt \$meminit} cells by the language frontend. +The \B{MEMID} parameter on these cells is used to link them together and to the RTLIL::Memory object they belong to. The rationale behind using separate cells for the individual ports versus creating a large multiport memory cell right in the language frontend is that |