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authorRuben Undheim <ruben.undheim@gmail.com>2014-09-06 08:47:06 +0200
committerRuben Undheim <ruben.undheim@gmail.com>2014-09-06 08:47:06 +0200
commit79cbf9067c07ed810b3466174278d77b9a05b46d (patch)
treeb546123251d39df2ffd115fb0b8a08e57e7cf538 /manual/CHAPTER_Prog/stubnets.cc
parent01ef34c147dd3e3e3d13864f9c726727a4013207 (diff)
Corrected spelling mistakes found by lintian
Diffstat (limited to 'manual/CHAPTER_Prog/stubnets.cc')
-rw-r--r--manual/CHAPTER_Prog/stubnets.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 4d1452c9..ef4b1245 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -57,7 +57,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// we will record which bits of the (possibly multi-bit) wire are stub signals
std::set<int> stub_bits;
- // get a signal description for this wire and split it into seperate bits
+ // get a signal description for this wire and split it into separate bits
RTLIL::SigSpec sig = sigmap(wire);
// for each bit (unless it is a constant):