path: root/manual/CHAPTER_Techmap.tex
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authorRuben Undheim <>2014-09-06 08:47:06 +0200
committerRuben Undheim <>2014-09-06 08:47:06 +0200
commit79cbf9067c07ed810b3466174278d77b9a05b46d (patch)
treeb546123251d39df2ffd115fb0b8a08e57e7cf538 /manual/CHAPTER_Techmap.tex
parent01ef34c147dd3e3e3d13864f9c726727a4013207 (diff)
Corrected spelling mistakes found by lintian
Diffstat (limited to 'manual/CHAPTER_Techmap.tex')
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex
index 26632d0b..e5c7456c 100644
--- a/manual/CHAPTER_Techmap.tex
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@@ -32,7 +32,7 @@ the Yosys source tree.
Additional features have been added to {\tt techmap} to allow for conditional
mapping of cells (see {\tt help techmap} or Sec.~\ref{cmd:techmap}). This can
-for example be usefull if the target architecture supports hardware multipliers for
+for example be useful if the target architecture supports hardware multipliers for
certain bit-widths but not for others.
A usual synthesis flow would first use the {\tt techmap} pass to directly map