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authorClifford Wolf <clifford@clifford.at>2014-02-16 14:32:56 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-16 14:32:56 +0100
commitaeb36b0b8b499a5b758840998afe9f1b4d7fc166 (patch)
tree79ad73d969f02df836461d23040659b596f8c1fb /manual/PRESENTATION_ExAdv/sym_mul_test.ys
parent9c29969bbc1b19f251011feaa791d242ac8e5e81 (diff)
Progress in presentation
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+read_verilog sym_mul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v;;
+
+show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v