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authorClifford Wolf <clifford@clifford.at>2015-07-02 11:14:30 +0200
committerClifford Wolf <clifford@clifford.at>2015-07-02 11:14:30 +0200
commit6c84341f22b2758181164e8d5cddd23e3589c90b (patch)
tree0438ad9becf956e43ebf8665fee89e021b13bcdf /manual/PRESENTATION_ExAdv
parent053058d78167f7f1ec377fddcee8b648a5ae4138 (diff)
Fixed trailing whitespaces
Diffstat (limited to 'manual/PRESENTATION_ExAdv')
-rw-r--r--manual/PRESENTATION_ExAdv/addshift_map.v8
-rw-r--r--manual/PRESENTATION_ExAdv/red_or3x1_map.v6
-rw-r--r--manual/PRESENTATION_ExAdv/sym_mul_map.v6
3 files changed, 10 insertions, 10 deletions
diff --git a/manual/PRESENTATION_ExAdv/addshift_map.v b/manual/PRESENTATION_ExAdv/addshift_map.v
index b6d91b01..13ecf0ba 100644
--- a/manual/PRESENTATION_ExAdv/addshift_map.v
+++ b/manual/PRESENTATION_ExAdv/addshift_map.v
@@ -4,17 +4,17 @@ module \$add (A, B, Y);
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
-
+
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-
+
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_A_ = 0;
parameter _TECHMAP_CONNMAP_B_ = 0;
-
+
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
-
+
assign Y = A << 1;
endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_map.v b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
index 24ca9dab..8c37b1db 100644
--- a/manual/PRESENTATION_ExAdv/red_or3x1_map.v
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
@@ -3,10 +3,10 @@ module \$reduce_or (A, Y);
parameter A_SIGNED = 0;
parameter A_WIDTH = 0;
parameter Y_WIDTH = 0;
-
+
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
-
+
function integer min;
input integer a, b;
begin
@@ -16,7 +16,7 @@ module \$reduce_or (A, Y);
min = b;
end
endfunction
-
+
genvar i;
generate begin
if (A_WIDTH == 0) begin
diff --git a/manual/PRESENTATION_ExAdv/sym_mul_map.v b/manual/PRESENTATION_ExAdv/sym_mul_map.v
index 293c5b84..b4dbd9e0 100644
--- a/manual/PRESENTATION_ExAdv/sym_mul_map.v
+++ b/manual/PRESENTATION_ExAdv/sym_mul_map.v
@@ -4,12 +4,12 @@ module \$mul (A, B, Y);
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
-
+
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
-
+
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
-
+
MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
endmodule