summaryrefslogtreecommitdiff
path: root/manual/PRESENTATION_ExOth.tex
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2014-06-14 16:42:30 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-14 16:45:16 +0200
commit1a487303a081849bd7561772641f90126dcce24e (patch)
tree8dee6bb844b53f78061fb48896995ea38c14e6ca /manual/PRESENTATION_ExOth.tex
parent22a998903b14b93180b98fe71129160e27793e38 (diff)
Progress in presentation
Diffstat (limited to 'manual/PRESENTATION_ExOth.tex')
-rw-r--r--manual/PRESENTATION_ExOth.tex66
1 files changed, 63 insertions, 3 deletions
diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex
index 13ec3d19..64c4af72 100644
--- a/manual/PRESENTATION_ExOth.tex
+++ b/manual/PRESENTATION_ExOth.tex
@@ -23,10 +23,70 @@ This section contains 3 subsections:
\subsectionpagesuffix
\end{frame}
-\subsubsection{TBD}
+\begin{frame}{\subsecname}
+Yosys can also be used to investigate designs (or netlists created
+from other tools).
-\begin{frame}{\subsubsecname}
-TBD
+\begin{itemize}
+\item
+The selection mechanism (see slides ``Using Selections''), especially pattern such
+as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
+are connected.
+
+\item
+Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
+to transform the design into an equivialent design that is easier to analyse.
+
+\item
+Commands such as {\tt eval} and {\tt sat} can be used to investigate the
+behavior of the circuit.
+\end{itemize}
+\end{frame}
+
+\begin{frame}[t, fragile]{Example: Reorganizing a module}
+\begin{columns}
+\column[t]{4cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExOth/scrambler.v}
+\column[t]{7cm}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]
+read_verilog scrambler.v
+
+hierarchy; proc;;
+
+cd scrambler
+submod -name xorshift32 xs %c %ci %D \
+ %c %ci:+[D] %D %ci*:-$dff \
+ xs %co %ci %d
+\end{lstlisting}
+\end{columns}
+
+\hfil\includegraphics[width=11cm,trim=0 0cm 0 1.5cm]{PRESENTATION_ExOth/scrambler_p01.pdf}
+
+\hfil\includegraphics[width=11cm,trim=0 0cm 0 2cm]{PRESENTATION_ExOth/scrambler_p02.pdf}
+\end{frame}
+
+\begin{frame}[t, fragile]{Example: Analysis of circuit behavior}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+> read_verilog scrambler.v
+> hierarchy; proc;; cd scrambler
+> submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
+
+> cd xorshift32
+> rename n2 in
+> rename n1 out
+
+> eval -set in 1 -show out
+Eval result: \out = 270369.
+
+> eval -set in 270369 -show out
+Eval result: \out = 67634689.
+
+> sat -set out 632435482
+Signal Name Dec Hex Bin
+-------------------- ---------- ---------- -------------------------------------
+\in 745495504 2c6f5bd0 00101100011011110101101111010000
+\out 632435482 25b2331a 00100101101100100011001100011010
+\end{lstlisting}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%