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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
| commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
| tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /manual/PRESENTATION_ExOth.tex | |
| parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
Fixed trailing whitespaces
Diffstat (limited to 'manual/PRESENTATION_ExOth.tex')
| -rw-r--r-- | manual/PRESENTATION_ExOth.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex index f86dcd7a..6bc44c5c 100644 --- a/manual/PRESENTATION_ExOth.tex +++ b/manual/PRESENTATION_ExOth.tex @@ -33,7 +33,7 @@ as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design are connected. \item -Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used +Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used to transform the design into an equivialent design that is easier to analyse. \item @@ -115,7 +115,7 @@ The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking. \end{frame} \begin{frame}[t]{Example: Formal Equivalence Checking (1/2)} -Remember the following example? +Remember the following example? \vskip1em \vbox to 0cm{ |