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authorClifford Wolf <clifford@clifford.at>2014-06-21 16:33:33 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-21 16:33:33 +0200
commitb18fa95d2f1f4118cdb7c16e3415059bd81e2325 (patch)
tree68ba5ef340312a0d5f3a63108dddf034e8e6dba6 /manual/PRESENTATION_ExOth/equiv.ys
parent1c85584fe5843a43590de3927fe9bde74a04e72e (diff)
Progress in presentation
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+# read test design
+read_verilog ../PRESENTATION_ExSyn/techmap_01.v
+hierarchy -top test
+
+# create two version of the design: test_orig and test_mapped
+copy test test_orig
+rename test test_mapped
+
+# apply the techmap only to test_mapped
+techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
+
+# create a miter circuit to test equivialence
+miter -equiv -make_assert -make_outputs test_orig test_mapped miter
+flatten miter
+
+# run equivialence check
+sat -verify -prove-asserts -show-inputs -show-outputs miter