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authorClifford Wolf <clifford@clifford.at>2015-07-02 11:14:30 +0200
committerClifford Wolf <clifford@clifford.at>2015-07-02 11:14:30 +0200
commit6c84341f22b2758181164e8d5cddd23e3589c90b (patch)
tree0438ad9becf956e43ebf8665fee89e021b13bcdf /manual/PRESENTATION_ExSyn.tex
parent053058d78167f7f1ec377fddcee8b648a5ae4138 (diff)
Fixed trailing whitespaces
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diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
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@@ -22,7 +22,7 @@
\item Convert remaining logic to bit-level logic functions
\item Perform optimizations on bit-level logic functions
\item Map bit-level logic gates and registers to cell library
-\item Write results to output file
+\item Write results to output file
\end{itemize}
\end{frame}