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author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /manual/PRESENTATION_ExSyn.tex | |
parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) |
Fixed trailing whitespaces
Diffstat (limited to 'manual/PRESENTATION_ExSyn.tex')
-rw-r--r-- | manual/PRESENTATION_ExSyn.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index b7d6b8a6..1230f32a 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -22,7 +22,7 @@ \item Convert remaining logic to bit-level logic functions \item Perform optimizations on bit-level logic functions \item Map bit-level logic gates and registers to cell library -\item Write results to output file +\item Write results to output file \end{itemize} \end{frame} |