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author | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:51:12 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-04 16:51:12 +0100 |
commit | 03d63dd861725ae9a4668a874566603b6b9bc247 (patch) | |
tree | a155d79656e02157daa5459760a84d162c961b70 /manual/PRESENTATION_ExSyn/abc_01_cells.v | |
parent | 7a5f378baef95bb1507333d86143662de1b08098 (diff) |
presentation progress
Diffstat (limited to 'manual/PRESENTATION_ExSyn/abc_01_cells.v')
-rw-r--r-- | manual/PRESENTATION_ExSyn/abc_01_cells.v | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/manual/PRESENTATION_ExSyn/abc_01_cells.v b/manual/PRESENTATION_ExSyn/abc_01_cells.v new file mode 100644 index 00000000..44409479 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/abc_01_cells.v @@ -0,0 +1,40 @@ + +module BUF(A, Y); +input A; +output Y = A; +endmodule + +module NOT(A, Y); +input A; +output Y = ~A; +endmodule + +module NAND(A, B, Y); +input A, B; +output Y = ~(A & B); +endmodule + +module NOR(A, B, Y); +input A, B; +output Y = ~(A | B); +endmodule + +module DFF(C, D, Q); +input C, D; +output reg Q; +always @(posedge C) + Q <= D; +endmodule + +module DFFSR(C, D, Q, S, R); +input C, D, S, R; +output reg Q; +always @(posedge C, posedge S, posedge R) + if (S) + Q <= 1'b1; + else if (R) + Q <= 1'b0; + else + Q <= D; +endmodule + |