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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-29 15:56:58 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-29 15:56:58 +0100 |
| commit | 34b39ec28a81818cda0a77c448819ecbf9da3cce (patch) | |
| tree | fd3427cd341c8957e75e921655e7d0b9929df7a5 /manual/PRESENTATION_Intro.tex | |
| parent | cbe77bf84465ea0c4120e865189b07329b862468 (diff) | |
presentation progress
Diffstat (limited to 'manual/PRESENTATION_Intro.tex')
| -rw-r--r-- | manual/PRESENTATION_Intro.tex | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 6693ad2f..6f3ea755 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -374,3 +374,35 @@ clean \includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf} \end{frame} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{More Yosys Commands} + +\begin{frame}{\subsecname{} -- TBD} +TBD +\end{frame} + +\subsection{More Verilog Examples} + +\begin{frame}{\subsecname{} -- TBD} +TBD +\end{frame} + +\subsection{Verification} + +\begin{frame}{\subsecname{} -- VlogHammer} +TBD +\end{frame} + +\begin{frame}{\subsecname{} -- yosys-bigsim} +TBD +\end{frame} + +\subsection{Benefits of Open Source HDL Synthesis} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + |