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authorClifford Wolf <clifford@clifford.at>2015-08-14 10:56:05 +0200
committerClifford Wolf <clifford@clifford.at>2015-08-14 10:56:05 +0200
commit84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch)
treec19a405bc106c2472f1aaa46c36b189db3e5223f /manual/PRESENTATION_Prog.tex
parent80910d13a610886f4430fbd991ada78b2e586ada (diff)
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@@ -124,7 +124,7 @@ has been executed.
\begin{frame}{\subsecname}
The RTLIL data structures are simple structs utilizing {\tt pool<>} and
-{\tt dict<>} containers (drop-in replacementments for {\tt
+{\tt dict<>} containers (drop-in replacements for {\tt
std::unordered\_set<>} and {\tt std::unordered\_map<>}).
\bigskip
@@ -413,7 +413,7 @@ When modifying existing modules, stick to the following DOs and DON'Ts:
\item Use {\tt module->fixup\_ports()} after changing the {\tt port\_*} properties of wires.
-\item You can safely remove cells or change the {\tt connetions} property of a cell, but be careful when
+\item You can safely remove cells or change the {\tt connections} property of a cell, but be careful when
changing the size of the {\tt SigSpec} connected to a cell port.
\item Use the {\tt SigMap} helper class (see next slide) when you need a unique handle for each signal bit.