summaryrefslogtreecommitdiff
path: root/manual/PRESENTATION_Prog
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
commitf9946232adf887e5aa4a48c64f88eaa17e424009 (patch)
tree39594b3287c3369752668456c4a6b1735fb66e77 /manual/PRESENTATION_Prog
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff)
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'manual/PRESENTATION_Prog')
-rw-r--r--manual/PRESENTATION_Prog/my_cmd.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index cf8a4add..0cd1da80 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -14,7 +14,7 @@ struct MyPass : public Pass {
log("Modules in current design:\n");
for (auto &mod : design->modules)
log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
- mod.second->wires.size(), mod.second->cells.size());
+ mod.second->wires_.size(), mod.second->cells.size());
}
} MyPass;
@@ -58,8 +58,8 @@ struct Test2Pass : public Pass {
RTLIL::Module *module = design->modules.at("\\test");
- RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
- y(module->wires.at("\\y"));
+ RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
+ y(module->wires_.at("\\y"));
log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
SigMap sigmap(module);