diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
| commit | 924d9d6e86a5e9a2294479345daac1c03d78008a (patch) | |
| tree | 04d28a2068b32c44c0aca2b8b815f6fc51cec427 /manual | |
| parent | ec92c8965960fa814c3663e987bc2a7eb80965e5 (diff) | |
Added read-enable to memory model
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 9f9ec2e2..c648eb1f 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -220,8 +220,9 @@ cell is created. Having individual cells for read and write ports has the advant consolidated using resource sharing passes. In some cases this drastically reduces the number of required ports on the memory cell. -The {\tt \$memrd} cells have a clock input \B{CLK}, an address input \B{ADDR} and a data output -\B{DATA}. They also have the following parameters: +The {\tt \$memrd} cells have a clock input \B{CLK}, an enable input \B{EN}, an +address input \B{ADDR}, and a data output \B{DATA}. They also have the +following parameters: \begin{itemize} \item \B{MEMID} \\ @@ -322,6 +323,9 @@ The {\tt \$mem} cell has the following ports: \item \B{RD\_CLK} \\ This input is \B{RD\_PORTS} bits wide, containing all clock signals for the read ports. +\item \B{RD\_EN} \\ +This input is \B{RD\_PORTS} bits wide, containing all enable signals for the read ports. + \item \B{RD\_ADDR} \\ This input is \B{RD\_PORTS}*\B{ABITS} bits wide, containing all address signals for the read ports. |