Fixed CRLF line endings

2 files changed, 297 insertions, 297 deletions

diff --git a/manual/literature.bib b/manual/literature.bib
index 91bc1f38..372e882a 100644
--- a/manual/literature.bib
+++ b/manual/literature.bib
@@ -1,163 +1,163 @@
-

-@inproceedings{intersynth,

-	title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},

-	author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},

-	booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},

-	pages={194--201},

-	year={2012}

-}

-

-@incollection{intersynthFdlBookChapter,

-	title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},

-	author={Johann Glaser and Clifford Wolf},

-	booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},

-	editor={Jan Haase},

-	publisher={Springer},

-	year={2013},

-	note={to appear}

-}

-

-@unpublished{BACC,

-	author = {Clifford Wolf},

-	title = {Design and Implementation of the Yosys Open SYnthesis Suite},

-	note = {Bachelor Thesis, Vienna University of Technology},

-	year = {2013}

-}

-

-@unpublished{VerilogFossEval,

-	author = {Clifford Wolf},

-	title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility},

-	note = {Unpublished Student Research Paper, Vienna University of Technology},

-	year = {2012}

-}

-

-@article{ABEL,

-	title={A High-Level Design Language for Programmable Logic Devices},

-	author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright},

-	journal={VLSI Design (Manhasset NY: CPM Publications)},

-	year={June 1985},

-	pages={50-62}

-}

-

-@MISC{Cheng93vl2mv:a,

-	author = {S-T Cheng and G York and R K Brayton},

-	title = {VL2MV: A Compiler from Verilog to BLIF-MV},

-	year = {1993}

-}

-

-@MISC{Odin,

-	author = {Peter Jamieson and Jonathan Rose},

-	title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS},

-	year = {2005}

-}

-

-@inproceedings{vtr2012,

-  title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing},

-  author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},

-  booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},

-  pages={77--86},

-  year={2012},

-  organization={ACM}

-}

-

-@MISC{LogicSynthesis,

-	author = {G D Hachtel and F Somenzi},

-	title = {Logic Synthesis and Verification Algorithms},

-	year = {1996}

-}

-

-@ARTICLE{Verilog2005, 

-	journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},

-	title={IEEE Standard for Verilog Hardware Description Language}, 

-	year={2006}, 

-	doi={10.1109/IEEESTD.2006.99495}

-}

-

-@ARTICLE{VerilogSynth, 

-	journal={IEEE Std 1364.1-2002},

-	title={IEEE Standard for Verilog Register Transfer Level Synthesis}, 

-	year={2002}, 

-	doi={10.1109/IEEESTD.2002.94220}

-}

-

-@ARTICLE{VHDL,

-	journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual},

-	year={2009},

-	month={26},

-	doi={10.1109/IEEESTD.2009.4772740}

-}

-

-@ARTICLE{VHDLSynth,

-	journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},

-	year={2004},

-	doi={10.1109/IEEESTD.2004.94802}

-}

-

-@ARTICLE{IP-XACT, 

-journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, 

-year={2010}, 

-pages={C1-360}, 

-keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, 

-doi={10.1109/IEEESTD.2010.5417309},}

-

-@book{Dragonbook,

-author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.},

-title = {Compilers: principles, techniques, and tools},

-year = {1986},

-isbn = {0-201-10088-6},

-publisher = {Addison-Wesley Longman Publishing Co., Inc.},

-address = {Boston, MA, USA},

-} 

-

-@INPROCEEDINGS{Cummings00,

-author = {Clifford E. Cummings and Sunburst Design Inc},

-title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill},

-booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper},

-year = {2000}

-}

-

-@ARTICLE{MURPHY,

-	author={D. L. Klipstein},

-	journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8},

-	title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects},

-	year={August 1967}

-}

-

-@INPROCEEDINGS{fsmextract, 

-author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, 

-booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, 

-title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, 

-year={2010}, 

-pages={2610-2613}, 

-keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, 

-doi={10.1109/ISCAS.2010.5537093},}

-

-@ARTICLE{MultiLevelLogicSynth, 

-author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, 

-journal={Proceedings of the IEEE}, 

-title={Multilevel logic synthesis}, 

-year={1990}, 

-volume={78}, 

-number={2}, 

-pages={264-300}, 

-keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, 

-doi={10.1109/5.52213}, 

-ISSN={0018-9219},}

-

-@article{UllmannSubgraphIsomorphism,

-	author = {Ullmann, J. R.},

-	title = {An Algorithm for Subgraph Isomorphism},

-	journal = {J. ACM},

-	issue_date = {Jan. 1976},

-	volume = {23},

-	number = {1},

-	month = jan,

-	year = {1976},

-	issn = {0004-5411},

-	pages = {31--42},

-	numpages = {12},

-	doi = {10.1145/321921.321925},

-	acmid = {321925},

-	publisher = {ACM},

-	address = {New York, NY, USA},

-} 

+
+@inproceedings{intersynth,
+	title={Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic},
+	author={Clifford Wolf and Johann Glaser and Florian Schupfer and Jan Haase and Christoph Grimm},
+	booktitle={FDL Proceeding of the 2012 Forum on Specification and Design Languages},
+	pages={194--201},
+	year={2012}
+}
+
+@incollection{intersynthFdlBookChapter,
+	title={Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures},
+	author={Johann Glaser and Clifford Wolf},
+	booktitle={Advances in Models, Methods, and Tools for Complex Chip Design --- Selected contributions from FDL'12},
+	editor={Jan Haase},
+	publisher={Springer},
+	year={2013},
+	note={to appear}
+}
+
+@unpublished{BACC,
+	author = {Clifford Wolf},
+	title = {Design and Implementation of the Yosys Open SYnthesis Suite},
+	note = {Bachelor Thesis, Vienna University of Technology},
+	year = {2013}
+}
+
+@unpublished{VerilogFossEval,
+	author = {Clifford Wolf},
+	title = {Evaluation of Open Source Verilog Synthesis Tools for Feature-Completeness and Extensibility},
+	note = {Unpublished Student Research Paper, Vienna University of Technology},
+	year = {2012}
+}
+
+@article{ABEL,
+	title={A High-Level Design Language for Programmable Logic Devices},
+	author={Kyu Y. Lee and Michael Holley and Mary Bailey and Walter Bright},
+	journal={VLSI Design (Manhasset NY: CPM Publications)},
+	year={June 1985},
+	pages={50-62}
+}
+
+@MISC{Cheng93vl2mv:a,
+	author = {S-T Cheng and G York and R K Brayton},
+	title = {VL2MV: A Compiler from Verilog to BLIF-MV},
+	year = {1993}
+}
+
+@MISC{Odin,
+	author = {Peter Jamieson and Jonathan Rose},
+	title = {A VERILOG RTL SYNTHESIS TOOL FOR HETEROGENEOUS FPGAS},
+	year = {2005}
+}
+
+@inproceedings{vtr2012,
+  title={The VTR Project: Architecture and CAD for FPGAs from Verilog to Routing},
+  author={Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
+  booktitle={Proceedings of the 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
+  pages={77--86},
+  year={2012},
+  organization={ACM}
+}
+
+@MISC{LogicSynthesis,
+	author = {G D Hachtel and F Somenzi},
+	title = {Logic Synthesis and Verification Algorithms},
+	year = {1996}
+}
+
+@ARTICLE{Verilog2005, 
+	journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
+	title={IEEE Standard for Verilog Hardware Description Language}, 
+	year={2006}, 
+	doi={10.1109/IEEESTD.2006.99495}
+}
+
+@ARTICLE{VerilogSynth, 
+	journal={IEEE Std 1364.1-2002},
+	title={IEEE Standard for Verilog Register Transfer Level Synthesis}, 
+	year={2002}, 
+	doi={10.1109/IEEESTD.2002.94220}
+}
+
+@ARTICLE{VHDL,
+	journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual},
+	year={2009},
+	month={26},
+	doi={10.1109/IEEESTD.2009.4772740}
+}
+
+@ARTICLE{VHDLSynth,
+	journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},
+	year={2004},
+	doi={10.1109/IEEESTD.2004.94802}
+}
+
+@ARTICLE{IP-XACT, 
+journal={IEEE Std 1685-2009}, title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, 
+year={2010}, 
+pages={C1-360}, 
+keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, 
+doi={10.1109/IEEESTD.2010.5417309},}
+
+@book{Dragonbook,
+author = {Aho, Alfred V. and Sethi, Ravi and Ullman, Jeffrey D.},
+title = {Compilers: principles, techniques, and tools},
+year = {1986},
+isbn = {0-201-10088-6},
+publisher = {Addison-Wesley Longman Publishing Co., Inc.},
+address = {Boston, MA, USA},
+} 
+
+@INPROCEEDINGS{Cummings00,
+author = {Clifford E. Cummings and Sunburst Design Inc},
+title = {Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill},
+booktitle = {SNUG (Synopsys Users Group) 2000 User Papers, section-MC1 (1 st paper},
+year = {2000}
+}
+
+@ARTICLE{MURPHY,
+	author={D. L. Klipstein},
+	journal={Cahners Publishing Co., EEE Magazine, Vol. 15, No. 8},
+	title={The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects},
+	year={August 1967}
+}
+
+@INPROCEEDINGS{fsmextract, 
+author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, 
+booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, 
+title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, 
+year={2010}, 
+pages={2610-2613}, 
+keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, 
+doi={10.1109/ISCAS.2010.5537093},}
+
+@ARTICLE{MultiLevelLogicSynth, 
+author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, 
+journal={Proceedings of the IEEE}, 
+title={Multilevel logic synthesis}, 
+year={1990}, 
+volume={78}, 
+number={2}, 
+pages={264-300}, 
+keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, 
+doi={10.1109/5.52213}, 
+ISSN={0018-9219},}
+
+@article{UllmannSubgraphIsomorphism,
+	author = {Ullmann, J. R.},
+	title = {An Algorithm for Subgraph Isomorphism},
+	journal = {J. ACM},
+	issue_date = {Jan. 1976},
+	volume = {23},
+	number = {1},
+	month = jan,
+	year = {1976},
+	issn = {0004-5411},
+	pages = {31--42},
+	numpages = {12},
+	doi = {10.1145/321921.321925},
+	acmid = {321925},
+	publisher = {ACM},
+	address = {New York, NY, USA},
+} 
diff --git a/manual/weblinks.bib b/manual/weblinks.bib
index 5215a6ca..d5f83315 100644
--- a/manual/weblinks.bib
+++ b/manual/weblinks.bib
@@ -1,134 +1,134 @@
-

-@misc{YosysGit,

-	author =       	{Clifford Wolf},

-	title =        	{{Yosys Open SYnthesis Suite (YOSYS)}},

-	note =		{\url{http://github.com/cliffordwolf/yosys}}

-}

-

-@misc{YosysTestsGit,

-	author =       	{Clifford Wolf},

-	title =        	{{Yosys Test Bench}},

-	note =		{\url{http://github.com/cliffordwolf/yosys-tests}}

-}

-

-@misc{VlogHammer,

-	author =       	{Clifford Wolf},

-	title =        	{{VlogHammer Verilog Synthesis Regression Tests}},

-	note =		{\url{http://github.com/cliffordwolf/VlogHammer}}

-}

-

-@misc{Icarus,

-	author =       	{Stephen Williams},

-	title =        	{{Icarus Verilog}},

-	note =		{Version 0.8.7, \url{http://iverilog.icarus.com/}}

-}

-

-@misc{VTR,

-	author=		{Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},

-	title =		{{The Verilog-to-Routing (VTR) Project for FPGAs}},

-	note =		{Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}

-}

-

-@misc{HANA,

-	author =       	{Parvez Ahmad},

-	title =        	{{HDL Analyzer and Netlist Architect (HANA)}},

-	note =		{Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}

-}

-

-@misc{MVSIS,

-	author =	{MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},

-	title =		{{MVSIS: Logic Synthesis and Verification}},

-	note =		{Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}

-}

-

-@misc{VIS,

-	author =	{{The VIS group}},

-	title =		{{VIS: A system for Verification and Synthesis}},

-	note =		{Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}

-}

-

-@misc{ABC,

-	author =	{{Berkeley Logic Synthesis and Verification Group}},

-	title =		{{ABC: A System for Sequential Synthesis and Verification}},

-	note =		{HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}

-}

-

-@misc{AIGER,

-	author =	{{Armin Biere, Johannes Kepler University Linz, Austria}},

-	title =		{{AIGER}},

-	note =		{\url{http://fmv.jku.at/aiger/}}

-}

-

-@misc{XilinxWebPACK,

-	author =	{{Xilinx, Inc.}},

-	title =		{{ISE WebPACK Design Software}},

-	note =		{\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}

-}

-

-@misc{QuartusWeb,

-	author =	{{Altera, Inc.}},

-	title =		{{Quartus II Web Edition Software}},

-	note =		{\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}

-}

-

-@misc{OR1200,

-	title =		{{OpenRISC 1200 CPU}},

-	note = 		{\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}

-}

-

-@misc{openMSP430,

-	title =		{{openMSP430 CPU}},

-	note = 		{\url{http://opencores.org/project,openmsp430}}

-}

-

-@misc{i2cmaster,

-	title =		{{OpenCores I$^2$C Core}},

-	note =		{\url{http://opencores.org/project,i2c}}

-}

-

-@misc{k68,

-	title =		{{OpenCores k68 Core}},

-	note =		{\url{http://opencores.org/project,k68}}

-}

-

-@misc{bison,

-	title = {{GNU Bison}},

-	note = {\url{http://www.gnu.org/software/bison/}}

-}

-

-@misc{flex,

-	title = {{Flex}},

-	note = {\url{http://flex.sourceforge.net/}}

-}

-

-@misc{C_to_Verilog,

-	title = {{C-to-Verilog}},

-	note = {\url{http://www.c-to-verilog.com/}}

-}

-

-@misc{LegUp,

-	title = {{LegUp}},

-	note = {\url{http://legup.eecg.utoronto.ca/}}

-}

-

-@misc{LibertyFormat,

-	title = {{The Liberty Library Modeling Standard}},

-	note = {\url{http://www.opensourceliberty.org/}}

-}

-

-@misc{ASIC-WORLD,

-	title = {{World of ASIC}},

-	note = {\url{http://www.asic-world.com/}}

-}

-

-@misc{Formality,

-	title = {{Synopsys Formality Equivalence Checking}},

-	note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},

-}

-

-@misc{bigint,

-	author = {Matt McCutchen},

-	title = {{C++ Big Integer Library}},

-	note = {\url{http://mattmccutchen.net/bigint/}}

-}

-

+
+@misc{YosysGit,
+	author =       	{Clifford Wolf},
+	title =        	{{Yosys Open SYnthesis Suite (YOSYS)}},
+	note =		{\url{http://github.com/cliffordwolf/yosys}}
+}
+
+@misc{YosysTestsGit,
+	author =       	{Clifford Wolf},
+	title =        	{{Yosys Test Bench}},
+	note =		{\url{http://github.com/cliffordwolf/yosys-tests}}
+}
+
+@misc{VlogHammer,
+	author =       	{Clifford Wolf},
+	title =        	{{VlogHammer Verilog Synthesis Regression Tests}},
+	note =		{\url{http://github.com/cliffordwolf/VlogHammer}}
+}
+
+@misc{Icarus,
+	author =       	{Stephen Williams},
+	title =        	{{Icarus Verilog}},
+	note =		{Version 0.8.7, \url{http://iverilog.icarus.com/}}
+}
+
+@misc{VTR,
+	author=		{Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
+	title =		{{The Verilog-to-Routing (VTR) Project for FPGAs}},
+	note =		{Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
+}
+
+@misc{HANA,
+	author =       	{Parvez Ahmad},
+	title =        	{{HDL Analyzer and Netlist Architect (HANA)}},
+	note =		{Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
+}
+
+@misc{MVSIS,
+	author =	{MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
+	title =		{{MVSIS: Logic Synthesis and Verification}},
+	note =		{Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
+}
+
+@misc{VIS,
+	author =	{{The VIS group}},
+	title =		{{VIS: A system for Verification and Synthesis}},
+	note =		{Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
+}
+
+@misc{ABC,
+	author =	{{Berkeley Logic Synthesis and Verification Group}},
+	title =		{{ABC: A System for Sequential Synthesis and Verification}},
+	note =		{HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
+}
+
+@misc{AIGER,
+	author =	{{Armin Biere, Johannes Kepler University Linz, Austria}},
+	title =		{{AIGER}},
+	note =		{\url{http://fmv.jku.at/aiger/}}
+}
+
+@misc{XilinxWebPACK,
+	author =	{{Xilinx, Inc.}},
+	title =		{{ISE WebPACK Design Software}},
+	note =		{\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
+}
+
+@misc{QuartusWeb,
+	author =	{{Altera, Inc.}},
+	title =		{{Quartus II Web Edition Software}},
+	note =		{\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
+}
+
+@misc{OR1200,
+	title =		{{OpenRISC 1200 CPU}},
+	note = 		{\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
+}
+
+@misc{openMSP430,
+	title =		{{openMSP430 CPU}},
+	note = 		{\url{http://opencores.org/project,openmsp430}}
+}
+
+@misc{i2cmaster,
+	title =		{{OpenCores I$^2$C Core}},
+	note =		{\url{http://opencores.org/project,i2c}}
+}
+
+@misc{k68,
+	title =		{{OpenCores k68 Core}},
+	note =		{\url{http://opencores.org/project,k68}}
+}
+
+@misc{bison,
+	title = {{GNU Bison}},
+	note = {\url{http://www.gnu.org/software/bison/}}
+}
+
+@misc{flex,
+	title = {{Flex}},
+	note = {\url{http://flex.sourceforge.net/}}
+}
+
+@misc{C_to_Verilog,
+	title = {{C-to-Verilog}},
+	note = {\url{http://www.c-to-verilog.com/}}
+}
+
+@misc{LegUp,
+	title = {{LegUp}},
+	note = {\url{http://legup.eecg.utoronto.ca/}}
+}
+
+@misc{LibertyFormat,
+	title = {{The Liberty Library Modeling Standard}},
+	note = {\url{http://www.opensourceliberty.org/}}
+}
+
+@misc{ASIC-WORLD,
+	title = {{World of ASIC}},
+	note = {\url{http://www.asic-world.com/}}
+}
+
+@misc{Formality,
+	title = {{Synopsys Formality Equivalence Checking}},
+	note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
+}
+
+@misc{bigint,
+	author = {Matt McCutchen},
+	title = {{C++ Big Integer Library}},
+	note = {\url{http://mattmccutchen.net/bigint/}}
+}
+