path: root/manual
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authorClifford Wolf <>2014-02-02 13:30:49 +0100
committerClifford Wolf <>2014-02-02 13:30:49 +0100
commit0f88e2869367966e6386cbe0b5e92ed028dae66c (patch)
tree32067c892638900a9ad3e333ba2c052bd0daa953 /manual
parent9334c341704e45c93f15157e3296b14cbf935ce3 (diff)
presentation progress
Diffstat (limited to 'manual')
2 files changed, 20 insertions, 10 deletions
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index 17830c6e..3440bbf1 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -203,14 +203,6 @@ TBD
-\subsection{Low-Level Synthesis}
\subsection{The ``techmap'' command}
diff --git a/manual/presentation.tex b/manual/presentation.tex
index bfd09a49..04998028 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -83,9 +83,27 @@
+Yosys is the first full-featured open source software for Verilog HDL
+synthesis. It supports most of Verilog-2005 and is well tested with
+real-world designs from the ASIC and FPGA world.
+Learn how to use Yosys to create your own custom synthesis flows and discover
+why open source HDL synthesis is important for researchers, hobbyists,
+educators and engineers alike.
+This presentation covers basic concepts of Yosys, creating simple synthesis
+scripts, creating synthesis scripts for advanced applications, creating Yosys
+scripts for non-synthesis applications (such as formal equivialence checking)
+and writing extensions to Yosys using the C++ API.
Yosys is an Open Source Verilog synthesis tool, and more.