path: root/manual
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authorClifford Wolf <>2013-11-28 13:48:38 +0100
committerClifford Wolf <>2013-11-28 13:48:38 +0100
commit6dfb66d26298662b4e64d55cf3c9f07738528ebc (patch)
tree836083510396a150cb6668637757609354047f4c /manual
parent5af7f4db72586a8cc8c1e685eb5af8f635e91718 (diff)
Started writing appnote 011
Diffstat (limited to 'manual')
6 files changed, 156 insertions, 2 deletions
diff --git a/manual/APPNOTE_011_Design_Investigation.tex b/manual/APPNOTE_011_Design_Investigation.tex
new file mode 100644
index 00000000..1dc9459f
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+++ b/manual/APPNOTE_011_Design_Investigation.tex
@@ -0,0 +1,134 @@
+% IEEEtran howto:
+\usepackage[T1]{fontenc} % required for luximono!
+\usepackage[scaled=0.8]{luximono} % typewriter font with bold face
+% To install the luximono font files:
+% getnonfreefonts-sys --all or
+% getnonfreefonts-sys luximono
+% when there are trouble you might need to:
+% - Create /etc/texmf/updmap.d/99local-luximono.cfg
+% containing the single line: Map
+% - Run update-updmap followed by mktexlsr and updmap-sys
+% This commands must be executed as root with a root environment
+% (i.e. run "sudo su" and then execute the commands in the root
+% shell, don't just prefix the commands with "sudo").
+\def\FIXME{{\color{red}\bf FIXME}}
+\title{Yosys Application Note 011: \\ Interactive Design Investigation}
+\author{Clifford Wolf \\ November 2013}
+Yosys \cite{yosys} can be a great environment for building custom synthesis
+flows \cite{glaserwolf}. It can also be an excellent tool for teaching and
+learning Verilog based RTL synthesis. In both applications it is of great
+importance to be able to analyze the designs produces easily.
+This Yosys application note covers the generation of circuit diagrams with the
+Yosys {\tt show} command and the selection of interesting parts of the circuit
+using the {\tt select} command.
+\section{Installation and Prerequisites}
+This Application Note is based on GIT Rev. {\tt \FIXME} from \FIXME{} of
+Yosys \cite{yosys}. The {\tt README} file covers how to install Yosys. The
+{\tt show} command requires a working installation of GraphViz \cite{graphviz}
+for generating the actual circuit diagrams. Yosys must be build with Qt
+support in order to activate the built-in SVG viewer. Alternatively an
+external viewer can be used.
+\section{Introduction to the {\tt show} command}
+$ cat example.ys
+read_verilog example.v
+show -pause
+show -pause
+show -pause
+$ cat example.v
+module example(input clk, a, b, c,
+ output reg [1:0] y);
+ always @(posedge clk)
+ if (c)
+ y <= c ? a + b : 2'd0;
+\caption{Synthesis script with added show commands and example code}
+\caption{\tt Output of the three show commands from Fig.~\ref{example_src}}
+Clifford Wolf. The Yosys Open SYnthesis Suite.
+Johann Glaser. Clifford Wolf. Methodology and Example-Driven Interconnect
+Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
+Architectures. In: Jan Haase (Editor). {\it Models, Methods, and Tools for Complex Chip Design.
+Lecture Notes in Electrical Engineering. Volume 265, 2014, pp 201-221.\/}
+\href{}{DOI 10.1007/978-3-319-01418-0\_12}
+Graphviz - Graph Visualization Software.
diff --git a/manual/APPNOTE_011_Design_Investigation/.gitignore b/manual/APPNOTE_011_Design_Investigation/.gitignore
new file mode 100644
index 00000000..6d396bb3
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+++ b/manual/APPNOTE_011_Design_Investigation/.gitignore
@@ -0,0 +1,3 @@
diff --git a/manual/APPNOTE_011_Design_Investigation/example.v b/manual/APPNOTE_011_Design_Investigation/example.v
new file mode 100644
index 00000000..ec272011
--- /dev/null
+++ b/manual/APPNOTE_011_Design_Investigation/example.v
@@ -0,0 +1,5 @@
+module example(input clk, a, b, c, output reg [1:0] y);
+always @(posedge clk)
+ if (c)
+ y <= c ? a + b : 2'd0;
diff --git a/manual/APPNOTE_011_Design_Investigation/example.ys b/manual/APPNOTE_011_Design_Investigation/example.ys
new file mode 100644
index 00000000..6c9ff798
--- /dev/null
+++ b/manual/APPNOTE_011_Design_Investigation/example.ys
@@ -0,0 +1,6 @@
+read_verilog example.v
+show -format dot -prefix example_00
+show -format dot -prefix example_01
+show -format dot -prefix example_02
diff --git a/manual/APPNOTE_011_Design_Investigation/ b/manual/APPNOTE_011_Design_Investigation/
new file mode 100644
index 00000000..31820695
--- /dev/null
+++ b/manual/APPNOTE_011_Design_Investigation/
@@ -0,0 +1,6 @@
+../../yosys example.ys
+sed -i '/^label=/ d;' example_*.dot
+dot -Tpdf -o example_00.pdf
+dot -Tpdf -o example_01.pdf
+dot -Tpdf -o example_02.pdf
diff --git a/manual/ b/manual/
index 00f87576..478e4cf9 100644
--- a/manual/
+++ b/manual/
@@ -1,10 +1,10 @@
set -ex
-for job in APPNOTE_010_Verilog_to_BLIF
+for job in APPNOTE_010_Verilog_to_BLIF APPNOTE_011_Design_Investigation
[ -f $job.ok -a $job.ok -nt $job.tex ] && continue
- old_md5=$([ -f $job.aux ] && md5sum < $job.aux)
+ old_md5=$([ -f $job.aux ] && md5sum < $job.aux || true)
pdflatex -shell-escape -halt-on-error $job.tex
new_md5=$(md5sum < $job.aux)