path: root/manual
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authorClifford Wolf <>2013-11-29 16:42:49 +0100
committerClifford Wolf <>2013-11-29 16:42:49 +0100
commit7295b25955ad6f185846e46e7a860e0b474f94a0 (patch)
tree57687bdfa28dcbd132cb5a4aa8976ce03cc22c05 /manual
parente23a0072ec75ce19733fb4ae04e623b17dbbd475 (diff)
Progress on AppNote 011
Diffstat (limited to 'manual')
5 files changed, 106 insertions, 16 deletions
diff --git a/manual/APPNOTE_011_Design_Investigation.tex b/manual/APPNOTE_011_Design_Investigation.tex
index 46485809..3a677354 100644
--- a/manual/APPNOTE_011_Design_Investigation.tex
+++ b/manual/APPNOTE_011_Design_Investigation.tex
@@ -206,18 +206,7 @@ of the circuit.
-module splice_demo(a, b, c, d, e, f, x, y);
-input [1:0] a, b, c, d, e, f;
-output [1:0] x = {a[0], a[1]};
-output [11:0] y;
-assign {y[11:4], y[1:0], y[3:2]} =
- {a, b, -{c, d}, ~{e, f}};
\caption{\tt splice.v}
@@ -441,11 +430,86 @@ this case this is also yields the diagram shown in Fig.~\ref{seladd}.
The output of {\tt help select} contains a complete syntax reference for
matching different properties.
-\subsection{Selecting logic cones}
+Many commands can operate on explicit selections. For example the command {\tt
+dump t:\$add} will print information on all {\tt \$add} cells in the active
+module. Whenever a command has {\tt [selection]} as last argument in its usage
+help, this means that it will use the engine behind the {\tt select} command
+to evaluate additional arguments and use the resulting selection instead of
+the selection performed by the last {\tt select} command.
+The command {\tt select -clear} can be used to reset the selection.
+\subsection{Operations on selections}
+\caption{Test module for operations on selections}
+The {\tt select} command is actually much more powerful than it might seem on
+the first glimpse. When it is called with multiple arguments, each argument is
+evaluated and pushed separately on a stack. After all arguments have been
+processed it simply creates the union of all elements on the stack. So the
+following command will select all {\tt \$add} cells and all objects with
+the {\tt foo} attribute set:
+select t:$add a:foo
+(Try this with the design shown in Fig.~\ref{foobaraddsub}. Use the {\tt
+select -list} command to list the current selection.)
+In many cases simply adding more and more stuff to the selection is an
+ineffective way of selecting the interesting part of the design. Special
+arguments can be used to differently combine the elements on the stack.
+For example the {\tt \%i} arguments intersects the last two elements on
+the stack. So the following command will select all {\$add} cells that
+have the {\tt foo} attribute set:
+select t:$add a:foo %i
+\caption{Another test module for operations on selections}
+The listing in Fig.~\ref{sumprod} used the Yosys non-standard {\tt \{* ... *\}}
+syntax to set the attribute {\tt sumstuff} on all cells generated by the first
+assign statement. (This works on arbitrary large blocks of Verilog code an
+can be used to mark portions of code for analysis.)
+\caption{Output of {\tt show a:sumstuff} on Fig.~\ref{sumprod}}
+Selecting {\tt a:sumstuff} in this module will yield the circuit diagram shown
+in Fig.~\ref{sumprod_00}. As only the cells themselves are selected, but not
+the temporary wire {\tt \$1\_Y}, the two adders are shown as two disjunct
+parts. This can be very useful for global signal like clock and reset signals: just
+unselect them using a command such as {\tt select -del clk rst} and each cell
+using them will get its own net label.
+In this case however we would like to see the cells connected properly. This
+can be achieved using the {\tt \%x} action, that broadens the selection, i.e.
+for each selected wire it selects all cells connected to the wire and vice
+versa. So {\tt show a:sumstuff \%x} yields the diagram schon in Fig.~\ref{sumprod_01}.
+\caption{Output of {\tt show a:sumstuff \%x} on Fig.~\ref{sumprod}}
-\subsection{Boolean operations on selections}
+\subsection{Selecting logic cones}
@@ -456,7 +520,7 @@ matching different properties.
\section{Advanced investigation techniques}
-\FIXME{} --- eval, sat
+\FIXME{} --- submod, eval, sat
diff --git a/manual/APPNOTE_011_Design_Investigation/.gitignore b/manual/APPNOTE_011_Design_Investigation/.gitignore
index 291bf026..5626754f 100644
--- a/manual/APPNOTE_011_Design_Investigation/.gitignore
+++ b/manual/APPNOTE_011_Design_Investigation/.gitignore
@@ -5,3 +5,5 @@
diff --git a/manual/APPNOTE_011_Design_Investigation/foobaraddsub.v b/manual/APPNOTE_011_Design_Investigation/foobaraddsub.v
new file mode 100644
index 00000000..0f277211
--- /dev/null
+++ b/manual/APPNOTE_011_Design_Investigation/foobaraddsub.v
@@ -0,0 +1,8 @@
+module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
+ input [7:0] a, b, c, d;
+ output [7:0] fa, fs, ba, bs;
+ assign fa = a + (* foo *) b;
+ assign fs = a - (* foo *) b;
+ assign ba = c + (* bar *) d;
+ assign bs = c - (* bar *) d;
diff --git a/manual/APPNOTE_011_Design_Investigation/ b/manual/APPNOTE_011_Design_Investigation/
index af08d990..cbabdc8e 100644
--- a/manual/APPNOTE_011_Design_Investigation/
+++ b/manual/APPNOTE_011_Design_Investigation/
@@ -3,7 +3,9 @@
../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v
../../yosys -p 'techmap; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -format dot -prefix cmos_00' cmos.v
../../yosys -p 'techmap; splitnets -ports; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -lib ../../techlibs/cmos/cmos_cells.v -format dot -prefix cmos_01' cmos.v
-sed -i '/^label=/ d;' example_*.dot cmos_*.dot
+../../yosys -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
+../../yosys -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
+sed -i '/^label=/ d;' example_*.dot cmos_*.dot sumprod_*.dot
dot -Tpdf -o example_00.pdf
dot -Tpdf -o example_01.pdf
dot -Tpdf -o example_02.pdf
@@ -11,3 +13,5 @@ dot -Tpdf -o example_03.pdf
dot -Tpdf -o splice.pdf
dot -Tpdf -o cmos_00.pdf
dot -Tpdf -o cmos_01.pdf
+dot -Tpdf -o sumprod_00.pdf
+dot -Tpdf -o sumprod_01.pdf
diff --git a/manual/APPNOTE_011_Design_Investigation/sumprod.v b/manual/APPNOTE_011_Design_Investigation/sumprod.v
new file mode 100644
index 00000000..4091bf0a
--- /dev/null
+++ b/manual/APPNOTE_011_Design_Investigation/sumprod.v
@@ -0,0 +1,12 @@
+module sumprod(a, b, c, sum, prod);
+ input [7:0] a, b, c;
+ output [7:0] sum, prod;
+ {* sumstuff *}
+ assign sum = a + b + c;
+ {* *}
+ assign prod = a * b * c;