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authorClifford Wolf <clifford@clifford.at>2014-02-06 14:01:43 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-06 14:01:43 +0100
commit821156b6cf27efd8a9b417433211b33c177917de (patch)
tree943149d47d8fae23c087f413dcf7cc2db7d77a5f /manual
parentc13c5b9b7b0925c602661bfcde8b45a538412f4b (diff)
presentation progress
Diffstat (limited to 'manual')
-rw-r--r--manual/PRESENTATION_ExAdv.tex83
-rw-r--r--manual/PRESENTATION_ExAdv/.gitignore1
-rw-r--r--manual/PRESENTATION_ExAdv/Makefile6
-rw-r--r--manual/PRESENTATION_ExAdv/select_01.v15
-rw-r--r--manual/PRESENTATION_ExAdv/select_01.ys10
-rw-r--r--manual/PRESENTATION_ExOth.tex23
-rw-r--r--manual/PRESENTATION_ExSyn.tex37
-rw-r--r--manual/PRESENTATION_Intro.tex78
-rw-r--r--manual/PRESENTATION_Prog.tex23
-rwxr-xr-xmanual/presentation.sh1
10 files changed, 265 insertions, 12 deletions
diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex
index 8457ceb7..21c5cdec 100644
--- a/manual/PRESENTATION_ExAdv.tex
+++ b/manual/PRESENTATION_ExAdv.tex
@@ -168,14 +168,66 @@ See {\tt help select} for full documentation of this expressions.
\subsubsection{Incremental selection}
-\begin{frame}{\subsubsecname}
-TBD
+\begin{frame}[fragile]{\subsubsecname}
+Sometime a selection can most easily described by a series of add/delete operations.
+For the commands {\tt select -add} and {\tt select -del} add or remove objects
+from the current selection instead of overwriting it.
+
+\medskip
+\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+select -none # start with an empty selection
+select -add reg_* # select a bunch of objects
+select -del reg_42 # but not this one
+select -add state %ci # and add mor stuff
+\end{lstlisting}
+
+\bigskip
+Within a select expression the token {\tt \%} can be used to push the previous selection
+on the stack.
+
+\medskip
+\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+select t:$add t:$sub # select all $add and $sub cells
+select % %ci % %d # select only the input wires to those cells
+\end{lstlisting}
\end{frame}
\subsubsection{Creating selection variables}
-\begin{frame}{\subsubsecname}
-TBD
+\begin{frame}[fragile]{\subsubsecname}
+Selections can be stored under a name with the {\tt select -set <name>}
+command. The stored selections can be used in later select expressions
+using the syntax {\tt @<name>}.
+
+\medskip
+\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+select -set cone_a state_a %ci*:-$dff # set @cone_a to the input cone of state_a
+select -set cone_b state_b %ci*:-$dff # set @cone_b to the input cone of state_b
+select @cone_a @cone_b %i # select the objects that are in both cones
+\end{lstlisting}
+
+\bigskip
+Remember that select expressions can also be used directly as arguments to most
+commands. Some commands also except a single select argument to some options.
+In those cases selection variables must be used to capture more complex selections.
+
+\medskip
+\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+dump @cone_a @cone_b
+
+select -set cone_ab @cone_a @cone_b %i
+show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
+\end{lstlisting}
+\end{frame}
+
+\begin{frame}[fragile]{\subsubsecname{} -- Example}
+\begin{columns}
+\column[t]{4cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/select_01.v}
+\column[t]{7cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys, frame=single]{PRESENTATION_ExAdv/select_01.ys}
+\end{columns}
+\hfil\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/select_01.pdf}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -225,3 +277,26 @@ TBD
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Summary}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item TBD
+\item TBD
+\item TBD
+\item TBD
+\end{itemize}
+
+\bigskip
+\bigskip
+\begin{center}
+Questions?
+\end{center}
+
+\bigskip
+\bigskip
+\begin{center}
+\url{http://www.clifford.at/yosys/}
+\end{center}
+\end{frame}
+
diff --git a/manual/PRESENTATION_ExAdv/.gitignore b/manual/PRESENTATION_ExAdv/.gitignore
new file mode 100644
index 00000000..cf658897
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/.gitignore
@@ -0,0 +1 @@
+*.dot
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
new file mode 100644
index 00000000..f38bd6ce
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -0,0 +1,6 @@
+
+all: select_01.pdf
+
+select_01.pdf: select_01.v select_01.ys
+ ../../yosys select_01.ys
+
diff --git a/manual/PRESENTATION_ExAdv/select_01.v b/manual/PRESENTATION_ExAdv/select_01.v
new file mode 100644
index 00000000..1b0bb7ee
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select_01.v
@@ -0,0 +1,15 @@
+module test(clk, s, a, y);
+ input clk, s;
+ input [15:0] a;
+ output [15:0] y;
+ reg [15:0] b, c;
+
+ always @(posedge clk) begin
+ b <= a;
+ c <= b;
+ end
+
+ wire [15:0] state_a = (a ^ b) + c;
+ wire [15:0] state_b = (a ^ b) - c;
+ assign y = !s ? state_a : state_b;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/select_01.ys b/manual/PRESENTATION_ExAdv/select_01.ys
new file mode 100644
index 00000000..a7fe2728
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select_01.ys
@@ -0,0 +1,10 @@
+read_verilog select_01.v
+hierarchy -check -top test
+proc; opt
+cd test
+select -set cone_a state_a %ci*:-$dff
+select -set cone_b state_b %ci*:-$dff
+select -set cone_ab @cone_a @cone_b %i
+show -prefix select_01 -format pdf -notitle \
+ -color red @cone_ab -color magenta @cone_a \
+ -color blue @cone_b
diff --git a/manual/PRESENTATION_ExOth.tex b/manual/PRESENTATION_ExOth.tex
index 8ac34f73..13ec3d19 100644
--- a/manual/PRESENTATION_ExOth.tex
+++ b/manual/PRESENTATION_ExOth.tex
@@ -61,3 +61,26 @@ TBD
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Summary}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item TBD
+\item TBD
+\item TBD
+\item TBD
+\end{itemize}
+
+\bigskip
+\bigskip
+\begin{center}
+Questions?
+\end{center}
+
+\bigskip
+\bigskip
+\begin{center}
+\url{http://www.clifford.at/yosys/}
+\end{center}
+\end{frame}
+
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index f84d3537..35d0b8a7 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -73,7 +73,7 @@ hierarchy -check -top top_module
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{The ``proc'' commands}
+\subsection{The {\tt proc} command}
\begin{frame}[fragile]{\subsecname}
The Verilog frontend converts {\tt always}-blocks to RTL netlists for the
@@ -137,7 +137,7 @@ after design elaboration.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{The ``opt'' commands}
+\subsection{The {\tt opt} command}
\begin{frame}[fragile]{\subsecname}
The {\tt opt} command implements a series of simple optimizations. It also
@@ -211,7 +211,7 @@ proc; opt; memory; opt_const;; fsm;;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{When to use ``opt'' or ``clean''}
+\subsection{When to use {\tt opt} or {\tt clean}}
\begin{frame}{\subsecname}
Usually it does not hurt to call {\tt opt} after each regular command in the
@@ -237,7 +237,7 @@ is a good idea in every synthesis script.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{The ``memory'' commands}
+\subsection{The {\tt memory} command}
\begin{frame}[fragile]{\subsecname}
In the RTL netlist, memory reads and writes are individual cells. This makes
@@ -291,7 +291,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{The ``fsm'' commands}
+\subsection{The {\tt fsm} command}
\begin{frame}[fragile]{\subsecname{}}
The {\tt fsm} command identifies, extracts, optimizes (re-encodes), and
@@ -343,7 +343,7 @@ Finally the {\tt fsm\_map} command can be used to convert the (optimized) {\tt
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{The ``techmap'' command}
+\subsection{The {\tt techmap} command}
\begin{frame}[t]{\subsecname}
\vbox to 0cm{\includegraphics[width=12cm,trim=-18cm 0cm 0cm -34cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
@@ -384,7 +384,7 @@ to map all RTL cell types to a generic library of built-in logic gates and regis
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{The ``abc'' command}
+\subsection{The {\tt abc} command}
\begin{frame}{\subsecname}
The {\tt abc} command provides an interface to ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}},
@@ -490,3 +490,26 @@ the next part (Section 3, ``Advanced Synthesis'') of this presentation.}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Summary}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Yosys provides commands for each phase of the synthesis.
+\item Each command solves a (more or less) simple problem.
+\item Complex command are often only front-ends to simple commands.
+\item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;}
+\end{itemize}
+
+\bigskip
+\bigskip
+\begin{center}
+Questions?
+\end{center}
+
+\bigskip
+\bigskip
+\begin{center}
+\url{http://www.clifford.at/yosys/}
+\end{center}
+\end{frame}
+
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 44657449..312cb898 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -466,7 +466,7 @@ Commands for high-level synthesis:
\bigskip
Commands for technology mapping:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
- techmap # simple technology mapper
+ techmap # generic technology mapper
abc # use ABC for technology mapping
dfflibmap # technology mapping of flip-flops
hilomap # technology mapping of constant hi- and/or lo-drivers
@@ -493,6 +493,14 @@ Script-Commands for standard synthesis tasks:
\end{lstlisting}
\bigskip
+Commands for model checking:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
+ sat # solve a SAT problem in the circuit
+ miter # automatically create a miter circuit
+ scc # detect strongly connected components (logic loops)
+\end{lstlisting}
+
+\bigskip
... and many many more.
\end{frame}
@@ -713,6 +721,51 @@ but also formal verification, reverse engineering, ...}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Other Open Source Tools}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Icarus Verilog \\
+\smallskip\hskip1cm{}Verilog Simulation (and also a good syntax checker) \\
+\smallskip\hskip1cm{}\url{http://iverilog.icarus.com/}
+
+\bigskip
+\item Qflow (incl. TimberWolf, qrouter and Magic) \\
+\smallskip\hskip1cm{}A complete ASIC synthesis flow, using Yosys and ABC \\
+\smallskip\hskip1cm{}\url{http://opencircuitdesign.com/qflow/}
+
+\bigskip
+\item ABC \\
+\smallskip\hskip1cm{}Logic optimization, technology mapping, and more \\
+\smallskip\hskip1cm{}\url{http://www.eecs.berkeley.edu/~alanmi/abc/}
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsection{What the Yosys project needs from you}
+
+\begin{frame}{\subsecname}
+We need you as an active user:
+\begin{itemize}
+\item Use Yosys for on your own designs
+\item .. even if you are not using it as final synthesis tool
+\item Join the discussion on the Subreddit
+\item Report bugs and send in feature requests
+\end{itemize}
+
+\bigskip
+We need you as a developer:
+\begin{itemize}
+\item Use Yosys as environment for your research work
+\item .. you might also want to look into ABC for logic-level stuff
+\item Fork the project on github or create loadable plugins
+\item We desperately need a VHDL frontend or a VHDL-to-Verilog converter
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
\subsection{Documentation, Downloads, Contatcs}
\begin{frame}{\subsecname}
@@ -736,3 +789,26 @@ but also formal verification, reverse engineering, ...}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Summary}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Yosys is a powerful tool and framework for Verilog synthesis.
+\item Is uses a command-based interface and can be controlled by scripts.
+\item By combining existing commands and implementing new commands Yosys can
+be used in a wide range of application far beyond simple synthesis.
+\end{itemize}
+
+\bigskip
+\bigskip
+\begin{center}
+Questions?
+\end{center}
+
+\bigskip
+\bigskip
+\begin{center}
+\url{http://www.clifford.at/yosys/}
+\end{center}
+\end{frame}
+
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index e9f86d0d..45f0cb0c 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -202,3 +202,26 @@ TBD
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Summary}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item TBD
+\item TBD
+\item TBD
+\item TBD
+\end{itemize}
+
+\bigskip
+\bigskip
+\begin{center}
+Questions?
+\end{center}
+
+\bigskip
+\bigskip
+\begin{center}
+\url{http://www.clifford.at/yosys/}
+\end{center}
+\end{frame}
+
diff --git a/manual/presentation.sh b/manual/presentation.sh
index 6719f916..6771ba7c 100755
--- a/manual/presentation.sh
+++ b/manual/presentation.sh
@@ -28,6 +28,7 @@ if ! $fast_mode; then
md5sum *.aux *.snm *.nav *.toc > autoloop.old
make -C PRESENTATION_Intro
make -C PRESENTATION_ExSyn
+ make -C PRESENTATION_ExAdv
fi
set -ex