path: root/manual
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authorClifford Wolf <>2014-01-03 00:22:17 +0100
committerClifford Wolf <>2014-01-03 00:22:17 +0100
commitfb2bf934dc6d2c969906b350c9a1b09a972bfdd7 (patch)
treeea47a664de2af51f09fe43f3040685438f5dd2ec /manual
parent536e20bde159db3ad8c77aeb9001a8dddde884a8 (diff)
Added correct handling of $memwr priority
Diffstat (limited to 'manual')
1 files changed, 3 insertions, 0 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 61713e74..b84e1b30 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -272,6 +272,9 @@ the \B{CLK} input is not used.
\item \B{CLK\_POLARITY} \\
Clock is active on positive edge if this parameter has the value {\tt 1'b1} and on the negative
edge if this parameter is {\tt 1'b0}.
+\item \B{PRIORITY} \\
+The cell with the higher integer value in this parameter wins a write conflict.
The HDL frontend models a memory using RTLIL::Memory objects and asynchronous