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authorClifford Wolf <clifford@clifford.at>2014-07-26 20:12:50 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 20:12:50 +0200
commit946ddff9cef3ea0b4dad8664319fb13074133775 (patch)
treee35f5ebe3cd76a8e10fe945872e32c2ed3a7d815 /passes/abc/blifparse.cc
parentd49dec1f861ce11a87c48cc21c8edc1755802a5f (diff)
Changed a lot of code to the new RTLIL::Wire constructors
Diffstat (limited to 'passes/abc/blifparse.cc')
-rw-r--r--passes/abc/blifparse.cc22
1 files changed, 6 insertions, 16 deletions
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index 45a9ac76..e86afa1b 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -98,14 +98,12 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
char *p;
while ((p = strtok(NULL, " \t\r\n")) != NULL) {
- RTLIL::Wire *wire = new RTLIL::Wire;
- wire->name = stringf("\\%s", p);
+ RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
wire->port_id = ++port_count;
if (!strcmp(cmd, ".inputs"))
wire->port_input = true;
else
wire->port_output = true;
- module->add(wire);
}
continue;
}
@@ -115,17 +113,11 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
char *d = strtok(NULL, " \t\r\n");
char *q = strtok(NULL, " \t\r\n");
- if (module->wires.count(RTLIL::escape_id(d)) == 0) {
- RTLIL::Wire *wire = new RTLIL::Wire;
- wire->name = RTLIL::escape_id(d);
- module->add(wire);
- }
+ if (module->wires.count(RTLIL::escape_id(d)) == 0)
+ module->addWire(RTLIL::escape_id(d));
- if (module->wires.count(RTLIL::escape_id(q)) == 0) {
- RTLIL::Wire *wire = new RTLIL::Wire;
- wire->name = RTLIL::escape_id(q);
- module->add(wire);
- }
+ if (module->wires.count(RTLIL::escape_id(q)) == 0)
+ module->addWire(RTLIL::escape_id(q));
RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
cell->set("\\D", module->wires.at(RTLIL::escape_id(d)));
@@ -162,9 +154,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
if (module->wires.count(stringf("\\%s", p)) > 0) {
wire = module->wires.at(stringf("\\%s", p));
} else {
- wire = new RTLIL::Wire;
- wire->name = stringf("\\%s", p);
- module->add(wire);
+ wire = module->addWire(stringf("\\%s", p));
}
input_sig.append(wire);
}