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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:18:00 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:18:30 +0200
commit10e5791c5e5660cb784503d36439ee90d61eb06b (patch)
treed7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/abc
parentd088854b47f5f77c6a62be2ba4b895164938d7a2 (diff)
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/abc')
-rw-r--r--passes/abc/abc.cc4
-rw-r--r--passes/abc/blifparse.cc2
2 files changed, 3 insertions, 3 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 7ba9424e..03fc9f93 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -684,7 +684,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
free(p);
log_header("Re-integrating ABC results.\n");
- RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"];
+ RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `netlist'.\n");
for (auto &it : mapped_mod->wires_) {
@@ -1000,7 +1000,7 @@ struct AbcPass : public Pass {
if (!constr_file.empty() && liberty_file.empty())
log_cmd_error("Got -constr but no -liberty!\n");
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
if (mod_it.second->processes.size() > 0)
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index 773bbe5d..4bcbc013 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
int port_count = 0;
module->name = "\\netlist";
- design->modules[module->name] = module;
+ design->modules_[module->name] = module;
size_t buffer_size = 4096;
char *buffer = (char*)malloc(buffer_size);