Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

1 files changed, 2 insertions, 2 deletions

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index d2be7dcf..d204e93c 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -313,7 +313,7 @@ static void handle_loops()
 			}
 
 			std::stringstream sstr;
-			sstr << "$abcloop$" << (RTLIL::autoidx++);
+			sstr << "$abcloop$" << (autoidx++);
 			RTLIL::Wire *wire = module->addWire(sstr.str());
 
 			bool first_line = true;
@@ -400,7 +400,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 		std::string liberty_file, std::string constr_file, bool cleanup, int lut_mode, bool dff_mode, std::string clk_str, bool keepff)
 {
 	module = current_module;
-	map_autoidx = RTLIL::autoidx++;
+	map_autoidx = autoidx++;
 
 	signal_map.clear();
 	signal_list.clear();